CS8900-CQ 查看數據表（PDF） - Cirrus Logic

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CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

faults, the host should clear the transmit buffer.

Possible options include:

Reset the chip with either software or hardware

reset (see Section 3.3).

Issue a Force Transmit Command by setting the

Force bit (Register 9, TxCMD, bit 8).

Issue a Transmit Command with the TxLength

field set to zero.

Transmit Collision: The MAC counts the num-

ber of times an individual packet must be

re-transmitted due to network collisions. The col-

lision count is stored in bits B through E of the

TxEvent register (Register 8). If the packet col-

lides 16 times, transmission of that packet is

terminated and the 16coll bit (Register 8,

TxEvent, Bit F) is set. If the 16colliE bit (Regis-

ter 7, TxCFG, Bit F) is set, the host will be

interrupted on the 16th collision. A running

count of transmit collisions is recorded in the

TxCOL register.

Transmit Underrun: If the CS8900 starts trans-

mission of a packet but runs out of data before

reaching the end of frame, the TxUnderrun bit

(Register C, BufEvent, Bit 9) is set. The MAC

then forces a bad CRC and terminates the trans-

mission. If the TxUnderruniE bit (Register B,

BufCFG, Bit 9) is set, the host is interrupted.

Receive Error Detection and Handling

The following receive errors are reported in the

RxEvent register (Register 4):

CRC Error: If a frame is received with a bad

CRC, the CRCerror bit (Register 4, RxEvent, Bit

C) is set. If the CRCerrorA bit (Register 5,

RxCTL, Bit C) is set, the frame will be buffered

by CS8900. If the CRCerroriE bit (Register 3,

RxCFG. Bit C) is set, the host is interrupted.

Runt Frame: If a frame is received that is

shorter than 64 bytes, the Runt bit (Register 4,

RxEvent, Bit D) is set. If the RuntA bit (Register

5, RxCTL, Bit D) is set, the frame will still be

buffered by CS8900. If the RuntiE bit (Register

3, RxCFG. Bit D) is set, the host is interrupted.

Extra Data: If a frame is received that is longer

than 1518 bytes, the Extradata bit (Register 4,

RxEvent, Bit E) is set. If the ExtradataA bit

(Register 5, RxCTL, Bit E) is set, the first 1518

bytes of the frame will still be buffered by

CS8900. If the ExtradataiE bit (Register 3,

RxCFG. Bit E) is set, the host is interrupted.

Dribble Bits and Alignment Error: Under nor-

mal operating conditions, the MAC may detect

up to 7 additional bits after the last full byte of a

receive packet. These bits, known as dribble bits,

are ignored. If dribble bits are detected, the Drib-

blebit bit (Register 4, RxEvent, Bit 7) is set. If

both the Dribblebit bit and CRCerror bit (Regis-

ter 4, RxEvent, Bit C) are set at the same time,

an alignment error has occurred.

Media Access Management

The Ethernet network topology is a single shared

medium with several attached stations. The Eth-

ernet protocol is designed to allow each station

equal access to the network at any given time.

Any node can attempt to gain access to the net-

work by first completing a deferral process

(described below) after the last network activity,

and then transmitting a packet that will be re-

ceived by all other stations. If two nodes

transmit simultaneously, a collision occurs and

the colliding packets are corrupted. Two primary

tasks of the MAC are to avoid network colli-

sions, and then recover from them when they

occur. In addition, when the CS8900 is using the

AUI, the MAC must support the SQE Test func-

tion described in section 7.2.4.6 of the Ethernet

standard.

DS150PP2

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