CS8900-CQ 查看數據表（PDF） - Cirrus Logic

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CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

LED Connection

Each LED output is capable of sinking 10 mA to

drive an LED directly through a series resistor.

The output voltage of each pin is less than 0.4 V

when the pin is low. Figure 3.4 shows a typical

LED circuit.

+5V

LANLED

LINKLED

Figure 3.4. LED Connection Diagram

3.9 Media Access Control

Overview

The CS8900’s Ethernet Media Access Control

(MAC) engine is fully compliant with the IEEE

802.3 Ethernet standard (ISO/IEC 8802-3, 1993).

It handles all aspects of Ethernet frame transmis-

sion and reception, including: collision detection,

preamble generation and detection, and CRC

generation and test. Programmable MAC fea-

tures include automatic retransmission on

collision, and padding of transmitted frames.

LED

Logic

CS8900

Internal Bus

802.3

MAC

Engine

Encoder/

Decoder

&

PLL

10BASE-T

& AUI

Figure 3.5. MAC Interface

DS150PP2

Figure 3.5 shows how the MAC engine inter-

faces to other CS8900 functions. On the host

side, it interfaces to the CS8900’s internal

data/address/control bus. On the network side, it

interfaces to the internal Manchester encoder/de-

coder (ENDEC). The primary functions of the

MAC are: frame encapsulation and decapsula-

tion; error detection and handling; and, media

access management.

Frame Encapsulation and Decapsulation

The CS8900’s MAC engine automatically assem-

bles transmit packets and disassembles receive

packets. It also determines if transmit and re-

ceive frames are of legal minimum size.

Transmission: Once the proper number of bytes

have been transferred to the CS8900’s memory

(either 5, 381, 1021 bytes, or full frame), and

providing that access to the network is permitted,

the MAC automatically transmits the 7-byte pre-

amble (1010101b...), followed by the

Start-of-Frame Delimiter (SFD, 10101011b), and

then the serialized frame data. It then transmits

the Frame Check Sequence (FCS). The data after

the SFD and before the FCS (Destination Ad-

dress, Source Address, Length, and data field) is

supplied by the host. FCS generation by the

CS8900 may be disabled by setting the In-

hibitCRC bit (Register 9, TxCMD, bit C).

Figure 3.6 shows the Ethernet frame format.

Reception: The MAC receives the incoming

packet as a serial stream of NRZ data from the

Manchester encoded/decoder. It begins by check-

ing for the SFD. Once the SFD is detected, the

MAC assumes all subsequent bits are frame data.

It reads the DA and compares it to the criteria

programmed into the address filter (see Section

5.3 for a description of Address Filtering). If the

DA passes the address filter, the frame is loaded

into the CS8900’s memory. If the BufferCRC bit

(Register 3, RxCFG, bit B) is set, the received

FCS is also loaded into memory. Once the en-

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