CS4812 查看數據表（PDF） - Cirrus Logic
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CS4812 Datasheet PDF : 36 Pages
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CS4812
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C® MASTER (TA = 25°C;
VA, VD = 5V; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30 pF)
Parameter
Symbol
Min
Typ
Max Units
I2C® Master (AutoBoot) Mode (SPI/I2C = 1, SCPM/S = 1) (Note 21)
SCL Clock Frequency
(Note 22)
fscl
Clock Low Time
tlow
Clock High Time
thigh
Bus Free Time Between Transmissions
tbuf
RST rising to start condition
tirs
Start Condition Hold Time
thdst
Setup Time for Repeated Start Condition
tsust
SDA Setup Time to SCL Rising
tsud
SDA Hold Time from SCL Falling
(Note 23) thdd
SCL falling to SDA Output Valid
tcldv
SCL and SDA Rise Time
(Note 24)
tr
SCL and SDA Fall Time
(Note 24)
tf
Setup Time for Stop Condition
tsusp
-
Fs
-
kHz
-
1/(2*Fs)
-
µs
-
1/(2*Fs)
-
µs
4.7
-
-
µs
-
22
-
µs
4.0
-
-
µs
13.5
-
-
µs
250
-
-
ns
0
-
-
µs
-
-
1.5
µs
-
-
1
µs
-
-
300
ns
4.7
-
-
µs
Notes: 21. Use of the I2C bus interface requires a license from Philips. I2C is a registered trademark of Philips
Semiconductors.
22. Depending on the input clock configuration, CCLK may be up to 2*Fs temporarily during AutoBoot after
RST has been de-asserted and before the control port registers have been initialized.
23. Data must be held for sufficient time to bridge the worst case fall time of 300 ns for CCLK/SCL.
24. For both SDA transmitting and receiving.
RST
t irs
Stop
Start
tcldv
Repeated
Start
SDA
t buf
t hdst
t high
t hdst
tf
SCL
(output)
t low t hdd
t sud
t sust
tr
Figure 4. I2C® Control Port Master Mode (AutoBoot) Timing
Stop
t susp
12
DS291PP3
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