AT89C51CC03C-RLTIM 查看數據表（PDF） - Atmel Corporation
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AT89C51CC03C-RLTIM Datasheet PDF : 197 Pages
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AT89C51CC03
Bit Number
Bit Mnemonic
3
CPOL
2
CPHA
1
SPR1
0
SPR0
Reset Value = 0001 0100b
Not bit addressable
Description
Clock Polarity
Cleared to have the SCK set to ’0’ in idle state.
Set to have the SCK set to ’1’ in idle state.
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle
state (see CPOL).
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
SPR2
0
0
0
0
1
1
1
1
SPR1
0
0
1
1
0
0
1
1
SPR0 Serial Peripheral Rate
0
Invalid
1
FCLK PERIPH /4
0
FCLK PERIPH /8
1
FCLK PERIPH /16
0
FCLK PERIPH /32
1
FCLK PERIPH /64
0
FCLK PERIPH /128
1
Invalid
Serial Peripheral Status Register
and Control (SPSCR)
The Serial Peripheral Status Register contains flags to signal the following conditions:
• Data transfer complete
• Write collision
• Inconsistent logic level on SS pin (mode fault error)
Table 93. SPSCR Register
SPSCR - Serial Peripheral Status and Control register (0D5H)
7
6
5
4
3
2
SPIF
-
OVR
MODF
SPTE
UARTM
1
SPTEIE
0
MODFIE
Bit
Bit
Number Mnemonic Description
Serial Peripheral Data Transfer Flag
Cleared by hardware to indicate data transfer is in progress or has been
7
SPIF approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
This bit is cleared when reading or writing SPDATA after reading SPSCR.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Overrun Error Flag
5
OVR
- Set by hardware when a byte is received whereas SPIF is set (the previous
received data is not overwritten).
- Cleared by hardware when reading SPSCR
4182K–CAN–05/06
139
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