AT89C51CC03C-RLTIM 查看數據表（PDF） - Atmel Corporation

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AT89C51CC03C-RLTIM

Enhanced 8-bit MCU with CAN Controller and Flash Memory

Atmel Corporation 

Functional Description Figure 58 shows a detailed structure of the SPI Module.

Figure 58. SPI Module Block Diagram

Internal Bus

SPDAT

Transmit Data Register

Shift Register

7 65 4 3210

SPSCR SPIF

- OVR MODF SPTE UARTM SPTEIE MODFIE

Receive Data Register

Pin

Control

Logic

MOSI

MISO

SPI

Control

Clock

Logic

SCK

M

SS

S

SPCON SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

FCLK

PERIPH

SPI Interrupt

Request

8-bit bus

1-bit signal

Operating Modes

The Serial Peripheral Interface can be configured in one of the two modes: Master mode

or Slave mode. The configuration and initialization of the SPI Module is made through

two registers:

• The Serial Peripheral Control register (SPCON)

• The Serial Peripheral Status and Control Register (SPSCR)

Once the SPI is configured, the data exchange is made using:

• The Serial Peripheral DATa register (SPDAT)

During an SPI transmission, data is simultaneously transmitted (shifted out serially) and

received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sam-

pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows

individual selection of a Slave SPI device; Slave devices that are not selected do not

interfere with SPI bus activities.

132 AT89C51CC03

4182K–CAN–05/06

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