
17.2.11 TBS_CFG - 0x2A
CS5376
Figure 80. Test Bit Stream Configuration Register TBS_CFG
(MSB) 23
INTP7
R/W
0
22
INTP6
R/W
0
15
14
--
RATE2
R/W
R/W
0
0
7
LOOP
R/W
0
6
RUN
R/W
0
21
INTP5
R/W
0
13
RATE1
R/W
0
5
DDLY5
R/W
0
20
INTP4
R/W
0
12
RATE0
R/W
0
4
DDLY4
R/W
0
19
INTP3
R/W
0
11
--
R/W
0
3
DDLY3
R/W
0
18
INTP2
R/W
0
10
CDLY2
R/W
0
2
DDLY2
R/W
0
17
INTP1
R/W
0
9
CDLY1
R/W
0
1
DDLY1
R/W
0
16
INTP0
R/W
0
8
CDLY0
R/W
0
(LSB) 0
DDLY0
R/W
0
I/O Address: 0x2A
--
Not defined;
read as 0
R
Readable
W
Writable
R/W Readable and
Writable
Bits in bottom rows
are reset condition
Bit definitions:
23:16 INTP[7:0]
Interpolation factor 15 --
reserved
7
0xFF: 256
0xFE: 255
...
0x01: 2
0x00: 1 (use once)
6
14:12 RATE[2:0]
TBS internal clock 5:0
rate
111: 16.384 MHz
110: 8.192 MHz
101: 4.096 MHz
100: 2.048 MHz
011: 1.024 MHz
010: 512 kHz
001: 256 kHz
000: 32 kHz
(default)
Output bit rate is 1/8
of this frequency
LOOP
RUN
DDLY[5:0
Enable Test Bit
Stream Digital
Loopback
Enable Test Bit
Stream
Data output bit
delay
0x3F: 63 bits
0x3E: 62 bits
.
.
.
0x01: 1 bit
0x00: 0 bits (i.e. no
delay)
11 --
reserved
10:8 CDLY[2:0] Clock output phase
delay
111: 7/8 period
110: 3/4 period
101: 5/8 period
100: 1/2 period
011: 3/8 period
010: 1/4 period
001: 1/8 period
000: none
DS256PP1
110