CS5376-BS 查看數據表（PDF） - Cirrus Logic

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CS5376-BS

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

16. WATCHDOG TIMER

A watchdog timer built into the CS5376 can pro-

vide additional system robustness by monitoring

the decimation engine to ensure no unrecoverable

errors occur. If a programmed time period elapses

without the decimation engine automatically re-

starting the watchdog countdown timer, the

CS5376 performs a hardware reset. A hardware re-

set re-boots the system from EEPROM or re-en-

ables communication with the microcontroller,

depending on the boot mode selection.

16.1 Watchdog Timer Initialization

The watchdog timer is initialized by writing two

register values. First, the countdown timer clock

rate is selected in the CONFIG register (0x00), be-

tween 8.192 MHz and 32 kHz. Next, a countdown

value is written to the WD_CFG register (0x2B) to

select the number of clock cycles that must pass be-

fore a hardware reset occurs. After writing the

countdown value, the watchdog timer automatical-

ly starts at the countdown value and rate selected.

A hardware reset is required to exit watchdog mode

once it has been enabled.

As an example, a 1kHz output word rate (1 ms out-

put interval) should allow several milliseconds to

pass before a hardware reset occurs. If the watch-

dog timer clock is set to 1.024 MHz in the CONFIG

register and a countdown value of 0x004000 is

written to the WD_CFG register, a time interval of

16 ms must pass to cause a hardware reset.

16.2 Watchdog Timer Restart

When enabled, the decimation engine restarts the

countdown timer after every filtering algorithm

calculation. Some SPI 1 burst write commands,

(Write FIR Coefficients, Write IIR Coefficients,

and Write TBS Data), do not restart the countdown

timer until after the command has completed. If the

watchdog timer is enabled and an SPI 1 burst write

command does not complete within the countdown

interval, the CS5376 will reset. This recovers the

CS5376 from a state where it expects burst data

that is never written by the microcontroller.

The rate at which the decimation engine automati-

cally restarts the countdown timer depends on the

CS5376 configuration. A faster decimation engine

clock rate and a shorter number of filter coeffi-

cients will restart the countdown timer more quick-

ly. In general, the watchdog timer should be set to

expire if several output data periods pass without

being restarted by the decimation engine.

Output

Word Rate

4 kHz

2 kHz

1 kHz

500 Hz

333.3 Hz

250 Hz

125 Hz

62.5 Hz

Output

Interval

0.25 ms

0.5 ms

1.0 ms

2.0 ms

3.0 ms

4.0 ms

8.0 ms

16.0 ms

Reset

Delay

4 ms

8 ms

16 ms

32 ms

48 ms

64 ms

128 ms

256 ms

Watchdog

Clock

1.024 MHz

1.024 MHz

1.024 MHz

1.024 MHz

1.024 MHz

512 kHz

256 kHz

256 kHz

Watchdog

Counter

0x001000

0x002000

0x004000

0x008000

0x00C000

0x008000

0x008000

0x00FFFF

Figure 63. Watchdog Timer Recommended Settings

DS256PP1

91

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