CS42L56 查看數據表（PDF） - Cirrus Logic
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CS42L56 Datasheet PDF : 92 Pages
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MCLKDIS
MCLK
MCLKPREDIV
1 0
2 1
MCLKDIV2
1 0
2 1
NOTE:
The SCLK divide ratios shown in the figure are not
accurate when MCLK is a multiple of 6 MHz. For
accurate SCLK frequency values please refer to
Table 3. “Serial Port Clock Ratio Settings” beginning on
page 47 and Note 21 on page 23.
CS42L56
RATIO[4:0]
125
128
136
187.5
192
250
256
272
375
384
500
512
544
750
768
01001
01000
01011
01101
01100
10001
10000
10011
10101
10100
11001
11000
11011
11100
11101
LRCK
SCK=MCK[1:0]
010
011
100
101
110
111
RATIO[4:2]
00
SCLK
10
11
Figure 31. Serial Port Timing in Master Mode
Referenced Control
Register Location
SCK=MCK[1:0] ....................
MKPREDIV...........................
MCLKDIV2...........................
MCLKDIS.............................
RATIO[4:0]...........................
“SCLK Equals MCLK” on page 60
“MCLK Pre-Divide” on page 60
“MCLK Divide” on page 61
“MCLK Disable” on page 61
“Clock Ratio” on page 62
48
DS851F2
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