CS42L56 查看數據表（PDF） - Cirrus Logic

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CS42L56

Ultralow Power, Stereo Codec with Class H Headphone Amp

Cirrus Logic 

Input

MAX[2:0]

CS42L56

Limiter

Volume

ATTACK/RELEASE SOUND

CUSHION

Output

(after Limiter)

MAX[2:0]

CUSH[2:0]

4.8 Serial Port Clocking

ARATE[5:0]

RRATE[5:0]

Figure 30. Peak Detect & Limiter

The CODEC serial audio interface port operates either as a slave or master. It accepts externally generated

clocks in Slave Mode (M/S = 0b) and will generate synchronous clocks derived from an input master clock

(MCLK) in Master Mode (M/S = 1b). The RATIO[4:0] bits need to be set appropriately according to the

clocks being used in the system for correct device functionality. Table 3. “Serial Port Clock Ratio Settings”

beginning on page 47 shows possible clock frequencies achievable by the CS42L56 serial port and pro-

vides a reference on how the RATIO[4:0] bits need to be configured for different clock ratios. Figure 31

shows how SCLK and LRCK are internally derived in Master Mode.

MCLK (MHz)

22.5792

(MKPREDIV=1b)

(MCLKDIV2=1b)

11.2896

(MKPREDIV=0b)

(MCLKDIV2=1b)

5.6448

(MKPREDIV=0b)

(MCLKDIV2=0b)

LRCK (kHz)

11.0250

22.0500

44.1000

11.0250

22.0500

44.1000

11.0250

22.0500

44.1000

MCLK/ LRCK

Clock Ratio

2048

1024

512

1024

512

256

512

256

128

SCLK (MHz)

0.7056

1.4112

2.8224

0.7056

1.4112

2.8224

0.7056

1.4112

2.8224

MCLK/SCLK

Clock Ratio

32

16

8

16

8

4

8

4

2

RATIO[4:0]

11000

10000

01000

11000

10000

01000

11000

10000

01000

Table 3. Serial Port Clock Ratio Settings

46

DS851F2

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