CS89712-CB 查看數據表（PDF） - Cirrus Logic

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CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

Function

Power

Management

State Control

DAI, Codec or

SSI2

Interface

(SeeTable 22 )

.

ADC

Interface

(SSI1)

Signal

Name

nPWRFL

BATOK

nEXTPWR

nBATCHG

nPOR

RUN

WAKEUP

nURESET

SSICLK

SSITXFR

SSITXDA

SSIRXDA

Signal

Description

F9

I Power fail input; active low, deglitched input to force system into the

Standby State (Note 1)

L14

I Main battery OK input; falling edge generates a FIQ, a low level in the

Standby State inhibits system start up; deglitched input (Note 2)

M13

I External power sense; must be driven low if the system is powered by

an external source

K13

I New battery sense; driven low if battery voltage falls below the "no-

battery" threshold; it is a deglitched input (Note 2)

M16

I Power-on reset input. This signal is not deglitched. When active it

completely resets the entire system, including all the RTC registers.

Upon power-up, the signal must be held active low for a minimum of

100 µsec after VDD has settled. During normal operation, nPOR

needs to be held low for at least one clock cycle of the selected clock

speed (i.e., when running at 74 MHz, the pulse width of nPOR needs

to be > 14 nsec).

Note that nURESET, TEST(0), TEST(1), PE(0), PE(1), PE(2),

DRIVE(0), DRIVE(1), DD(0), DD(1), DD(2), and DD(3) are all latched

on the rising edge of nPOR.

H1

O This pin is the RUN signal. The pin will be high when the system is

active or idle, low while in the Standby State. See Table 91.

F10

I Wake up is a deglitched input signal. It must be held high for at least

125 µsec to guarantee its detection. Once detected it forces the sys-

tem into the Operating State from the Standby State. It is only active

when the system is in the Standby State. This pin is ignored when the

system is in the Idle or Operating State. It is used to wakeup the sys-

tem after first power-up, or after software has forced the system into

the Standby State. WAKEUP will be ignored for up to two seconds

after nPOR goes HIGH. Therefore, the external WAKEUP logic must

be designed to allow it to rise and stay HIGH for at least 125 usec,

two seconds after nPOR goes HIGH. (Note 2)

H12

I User reset input; active low deglitched input from user reset button.

This pin is also latched upon the rising edge of nPOR and read along

with the input pins nTEST[0-1] to force the device into special test

modes. nURESET does not reset the RTC. (Note 2)

T3

I/O DAI/Codec/SSI2 clock signal

K9

I/O DAI/Codec/SSI2 serial data output frame/synchronization pulse out-

put

K10

O DAI/Codec/SSI2 serial data output

P5

I DAI/Codec/SSI2 serial data input

SSIRXFR

ADCCLK

nADCCS

ADCOUT

ADCIN

SMPCLK

L8

I/O SSI2 serial data input frame/synchronization pulse

DAI external clock input

M8

O Serial clock output

N6

O Chip select for ADC interface

T6

O Serial data output

R5

I Serial data input

N7

O Sample clock output

Table 90. External Signal Functions (Continued)

142

DS502PP2

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