CS89712-CB 查看數據表（PDF） - Cirrus Logic

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CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

3) The EmbeddedICE interface, which provides

communication between the host computer and

the EmbeddedICE macrocell

The EmbeddedICE macrocell is programmed, in a

serial fashion, through the TAP controller on the

ARM via the JTAG interface. The EmbeddedICE

macrocell is by default disabled to minimize power

usage, and must be enabled at boot-up to support

this functionality.

4.2.2 Functionality

The ICEBreaker module consists of two real-time

watchpoint units together with a control and status

register. One or both of the units can be pro-

grammed to halt the execution of the instructions

by the ARM processor. Execution is halted when

either a match occurs between the values pro-

grammed into the ICEBreaker and the values cur-

rently appearing on the address bus, data bus, and

the various control signals. Any bit can be masked

to remove it from the comparison. Either unit can

be programmed as a watchpoint (monitoring data

accesses) or a breakpoint (monitoring instruction

fetches).

Using one of these watchpoint units, an unlimited

number of software breakpoints (in RAM) can be

supported by substitution of the actual code.

Note:

The EXTERN[1:0] signals from the ICEBreaker

module are not wired out in this device. This

mechanism is used to allow watchpoints to be

dependent on an external event. This behavior

can be emulated in software via the ICEBreaker

control registers.

A more detailed description is available in the

ARM Software Development Toolkit User Guide

and Reference Manual. The ICEBreaker module

and its registers are fully described in the

“ARM7TDMI” Data Sheet.

DS502PP2

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