CS89712-CB 查看數據表（PDF） - Cirrus Logic

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CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

3.18.18 Test Control Register (TestCTL, address offset 0118h)

7

6

5:0

F

E

D

DisableLT

011001

FDX

C

B

A

9

8

Disable Backoff

RSVD

ENDEC loop

TestCTL controls the diagnostic test modes of the CS89712.

Bit

Description

011001: These bits provide an internal address used by the CS89712 to identify this as register

19, the Test Control Register.

DisableLT: When set, the 10BASE-T interface allows packet transmission and reception

regardless of the link status. DisableLT is used in conjunction with the LinkOK (Register 14,

LineST, Bit 7) as follows:

LinkOK

0

0

1

DisableLT

0

1

N/A

No packet transmission for reception allowed.

Transmitter sends link impulses.

DisableLT overrides LinkOK to allow packet

transmission and reception. Transmitter does not

send link pulses.

Disable has no meaning if LinkOK = 1.

ENDECloop: When set, the CS89712 enters internal loopback mode where the internal

Manchester encoder output is connected to the decoder input. The 10BASE-T are disabled.

When clear, the CS89712 is configured for normal operation

Disable Backoff: When set, the backoff algorithm is disabled. The CS89712 transmitter looks

only for completion of the inter packet gap before starting transmission. When clear, the back-

off algorithm is used.

FDX: When set, 10BASE-T full duplex mode is enabled and CRS (Register 14, LineST, Bit E)

is ignored. This bit must be set when performing loopback tests on the 10BASE-T port. When

clear, the CS89712 is configured for standard half-duplex 10BASE-T operation.

RSVD: Reserved; must be a “0” when writing to this register.

Table 83. Test Control

At reset, if no EEPROM is found by the CS89712, then the register has the following initial state. If an EEPROM is

found, then the register’s initial value may be set by the EEPROM. See Section 2.24, “Programming the EEPROM”.

Reset value is: 0000 0000 0001 1001

3.19 Initiate Transmit Registers

3.19.1 Transmit Command Request Register (TxCMD, address offset 144h)

7:6

5:0

F

TxStart

001001

E

D

TxPadDis

C

B

InhibitCRC

A

9

8

Onecoll

Force

The word written to offset 0144h tells the CS89712 how the next packet should be transmitted. Note that this Ether-

net Port location is write-only, and the written word can be read from Ethernet address offset 0108h. The

DS502PP2

133

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