CS89712-CB 查看數據表（PDF） - Cirrus Logic

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CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

3.15 SS2 Registers

3.15.1 SS2DR Synchronous Serial Interface 2 Data (address 0x8000.1500)

This is the 16-bit-wide data register for the full-duplex master / slave SSI2 synchronous serial interface. Writ-

ing data to this register will initiate a transfer. Writes need to be word writes and the bottom 16 bits are trans-

ferred to the TX FIFO. Reads will be 32 bits as well with the lower 16 bits containing RX data, and the upper

16-bits should be ignored. Although the interface is byte-oriented, data is written in two bytes at a time to

allow higher bandwidth transfer. It is up to the software to assemble the bytes for the data stream in an ap-

propriate manner.

All reads / writes to this register must be word reads / writes.

3.15.2 SS2POP Synchronous Serial Interface 2 Pop Residual Byte (address 0x8000.16C0)

This is a write-only location which will cause the contents of the RX shift register to be popped into the RX

FIFO, thus enabling a residual byte to be read. The data value written to this register is ignored. This location

should be used in conjunction with the RESVAL and RESFRM bits in the SYSFLG2 register.

3.16 DAI Registers

There are five registers within the DAI Interface; one control, three data, and one status register. The control

register is used to mask or unmask interrupt requests to service the DAI’s FIFOs, and to select whether an

on-chip or off-chip clock is used to drive the bit rate, and to enable / disable operation. The first pair of data

register addresses the top of the Right Channel Transmit FIFO and the bottom of the Right Channel Receive

FIFO. A read accesses the receive FIFOs, and a write the transmit FIFOs. Note that these are four physi-

cally separate FIFOs to allow full-duplex transmission. The status register contains bits which signal FIFO

overrun and underrun errors and transmit and receive FIFO service requests. Each of these status condi-

tions signal an interrupt request to the interrupt controller. The status register also flags when the transmit

FIFOs are not full when the receive FIFOs are not empty.

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DS502PP2

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