CS89712-CB 查看數據表（PDF） - Cirrus Logic

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CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

3.13.8 COEOI Codec End of Interrupt Location (address 0x8000.07C0)

A write to this location clears the sound interrupt (CSINT).

3.13.9 KBDEOI Keyboard End of Interrupt Location (address 0x8000.1700)

A write to this location clears the KBDINT keyboard interrupt.

3.13.10 SRXEOF End of Interrupt Location (address 0x8000.1600)

A write to this location clears the SSI2 RX FIFO overflow status bit.

3.14 State Control Registers

3.14.1 STDBY Enter the Standby State Location (address 0x8000.0840)

A write to this location will put the system into the Standby State by halting the main oscillator. A write to this

location while there is an active interrupt will have no effect.

Notes: 1. Before entering the Standby State, the LCD Controller should be disabled. The LCD controller

should be enabled on exit from the Standby State.

2. If the CS89712 is attempting to get into the Snooze/Standby State when there is a pending

interrupt request, it will not enter into the low power mode. The instruction will get executed, but

the processor will ignore the command.

3.14.2 SNOOZE Enter Snooze State location

A write to this location will put the system into the Snooze State. The main clock will not be stopped in this

state. It is required to continue displaying a reduced LCD buffer on the first few lines of the display, and the

DC pump block will continue to generate the drive signals for external DC converter circuitry. Otherwise,

clocks to all parts of the device will be disabled. The device will automatically switch the DRAMs into self

refresh if the RFSHEN bit is set in the DRAM refresh period register. All transitions to the Snooze State are

synchronized with DRAM cycles. A write to this location while there is an active interrupt will have no effect.

Before entering this state, the data to be displayed in Snooze State must be transferred under program con-

trol into the on-chip SRAM (see section on Snooze State), and the LCDCON register and frame buffer start

address must be reprogrammed accordingly. On exit from Snooze State (via enabled interrupt or wakeup

event) program execution will continue from the next instruction after the write to the SNOOZE location.

3.14.3 HALT Enter the Idle State Location (address 0x8000.0800)

A write to this location will put the system into the Idle State by halting the clock to the processor until an

interrupt is generated. A write to this location while there is an active interrupt will have no effect.

3.14.4 SNZDISP Snooze Mode Display Size

This register contains the number of words to be displayed from the on-chip SRAM in Snooze State, minus

1. It is a 13-bit register, allowing up to 816 K words to be displayed. Because the on-chip SRAM data is al-

ways displayed at 1-bit-per-pixel in the Snooze State, the value programmed into this register is the number

of pixels to be displayed divided by 32. For a half-size VGA screen the number of words to be programmed

is (640 x 240 x 1)/32 = 4.8 K words. This is the maximum value that should be programmed in this register

in Snooze State for a half-size VGA display. To avoid any possibility of ‘snow’ on the display when operating

at high frequency, this register should always be programmed with a minimum value of 7. Correct operation

is not guaranteed below this value. The number of pixels displayed should be divisible by the number of

pixels in a single line of the display.

DS502PP2

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