V96SSC-33LPB1 查看數據表（PDF） - QuickLogic Corporation

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V96SSC-33LPB1

HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 Sx/Jx AND PowerPC™ 401Gx PROCESSORS

QuickLogic Corporation 

V96SSC

BTYPE[1:0]

10

11

CPU Mode

i960Jx

(32 bit bus)

i960Jx

(16 bit bus)

Table 2: BTYPE[1:0] Pin Decoding

Boot Address

A[31, 26:24]=”1110”

A[31, 26:24]=”1110”

Description

32-bit data bus, BE[3:0] valid for current

cycle, processor uses 1X clock and V96SSC

uses 2X clock

32-bit data bus, BE3 and BE0 valid for cur-

rent cycle, processor uses 1X clock and

V96SSC uses 2X clock

In i960Sx systems, the low order address signals are latched internally from the AD[15:0] bus upon

assertion of ALE. The high-order address lines are demultiplexed on the i960Sx processor, and are

routed directly to the V96SSC’s high order address inputs. The i960Jx processor uses a 32-bit

multiplexed address/data bus, therefore for i960Jx bus accesses, the V96SSC latches the high order

address signals internally on the assertion of ALE.

All accesses to V96SSC’s internal registers are performed via the AD[15:0] lines. In 32-bit i960Jx

systems, the internal registers are typically accessed in a 32 bit region where access to the internal

registers is done by software 16 bits at a time (BTYPE="10"). Alternately, it can be mapped into a 16

bit region using BTYPE="11". While the V96SSC is internally a 16-bit device, it is capable of

supporting 32-bit memory and peripheral devices.

V96SSC also supports direct interface to PPC401Gx. When BTYPE=”01” then the boot address

matches that of the PPC401Gx. In this mode a cycle can be initiated with either an ALE or ADS pulse.

Since the PPC401Gx has only an ALE output and lacks an ADS (AS) pin, ADS on the V96SSC can be

tied high by a pull-up resistor.

2.2 Burst DRAM Controller

The V96SSC’s DRAM controller provides the following features:

• Support for fast page mode, extended data out, and Ramtron’s enhanced DRAM architectures

• Two DRAM banks of up to 64MByte each (128MBytes total)

• Programmable DRAM bank address base and size

• Programmable row/column multiplexing mode

• Programmable RASx and CASx timings

• Support for 16-bit and 32-bit DRAM arrays

• Support for extended burst cycles up to 256 bytes transactions in length

• Programmable page caching to eliminate RAS cycles for subsequent accesses to the same

DRAM page

• Programmable refresh counter

• 1-0-0-0 read and 0-0-0-0 write performance at 33MHz

The burst DRAM controller is designed to support traditional fast page mode DRAMs (FPM), the new

extended data out page mode DRAMs (EDO), and Ramtron’s ultra high-performance enhanced

DRAM (Ramtron EDRAM) devices. A wide variety of DRAM speeds and organizations may be

4

V96SSC Data Sheet Rev 2.3

Copyright © 1997, V3 Semiconductor Inc.

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