V96SSC-33LPB1 查看數據表（PDF） - QuickLogic Corporation

零件编号

产品描述 (功能)

生产厂家

V96SSC-33LPB1

HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 Sx/Jx AND PowerPC™ 401Gx PROCESSORS

QuickLogic Corporation 

V96SSC

Note:

1. The delay is from CPU Address valid or ALE if it comes first.

Derate given delays by 0.058 ns per pF of load in excess of 50pF.

2. Relative to CLK2 only when T_CACA_RD or T_CACA_WR equals 0.

3. tM = (1 CLK2 period) * (T_RACA+1).

4. tN = (1/2 CLK2 period) * (T_CACA_RD + 1) for Read or (1/2 CLK2 period)*(T_CACA_WR+1) for 0-wait states

write.

5. For Read Mode 2 and Write Mode 1 only.

6. For Write Mode 1 only.

7. For CAS Write Mode 0 and 1.

6.0 Revision History

Table 14: Revision History

Revision

Number

Date

Comments and Changes

2.3

11/97 First release of RevB1 data sheet.

2.2

10/96 Data Book revision.

2.1

08/96 Updated timing specification.

2.01

11/95

Fixed incorrect polarity on some ALE and RESOUT signals. Fixed W/R

description.

Final Data Sheet. All specifications guaranteed from actual silicon. DC input

2.0

11/95 levels changed to TTL compatible. Removed 16MHz and 20MHz timing specifi-

cation.

First released version of the data sheet. Some changes to AC and DC specifi-

1.2

03/95 cations and to waveforms. All future changes to the data sheet will be docu-

mented in detail in this section.

1.0

01/95

First pre-silicon revision of preliminary data sheet. Sent only to a limited num-

ber of customers.

USA:

2348G Walsh Ave.

Santa Clara CA 95051

Phone: (408)988-1050 Fax: (408)988-2601

Toll Free: (800)488-8410 (Canada and U.S. only)

World Wide Web: http://www.vcubed.com

20

V96SSC Data Sheet Rev 2.3

Copyright © 1997, V3 Semiconductor Inc.

Share Link: