M45PE10-VMN6TP 查看數據表（PDF） - Numonyx -> Micron

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M45PE10-VMN6TP

1-Mbit, page-erasable serial flash memory with byte-alterability and 75 MHz SPI bus interface

Numonyx -> Micron 

Power-up and power-down

7

Power-up and power-down

M45PE10

At power-up and power-down, the device must not be selected (that is Chip Select (S) must

follow the voltage applied on VCC) until VCC reaches the correct value:

● VCC(min) at power-up, and then for a further delay of tVSL

● VSS at power-down

A safe configuration is provided in Section 3: SPI modes.

To avoid data corruption and inadvertent write operations during power up, a power on reset

(POR) circuit is included. The logic inside the device is held reset while VCC is less than the

power on reset (POR) threshold value, VWI – all operations are disabled, and the device

does not respond to any instruction.

Moreover, the device ignores all write enable (WREN), page write (PW), page program (PP),

page erase (PE) and sector erase (SE) instructions until a time delay of tPUW has elapsed

after the moment that VCC rises above the VWI threshold. However, the correct operation of

the device is not guaranteed if, by this time, VCC is still below VCC(min). No write, program or

erase instructions should be sent until the later of:

● tPUW after VCC passed the VWI threshold

● tVSL after wrap round VCC passed the VCC(min) level

These values are specified in Table 6.

If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be

selected for read instructions even if the tPUW delay is not yet fully elapsed.

As an extra protection, the Reset (Reset) signal can be driven Low for the whole duration of

the power-up and power-down phases.

At power-up, the device is in the following state:

● The device is in the standby power mode (not the deep power-down mode)

● The write enable latch (WEL) bit is reset

● The write in progress (WIP) bit is reset

Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply.

Each device in a system should have the VCC line decoupled by a suitable capacitor close to

the package pins (generally, this capacitor is of the order of 100 nF).

At power-down, when VCC drops from the operating voltage, to below the power on reset

(POR) threshold value, VWI, all operations are disabled and the device does not respond to

any instruction (the designer needs to be aware that if a power-down occurs while a write,

program or erase cycle is in progress, some data corruption can result).

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