ST7PMC2N6B6(2004) 查看數據表（PDF） - STMicroelectronics

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ST7PMC2N6B6
(Rev.:2004)

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI™

STMicroelectronics 

ST7MC1/ST7MC2

11.8 I/O PORT PIN CHARACTERISTICS

11.8.1 General Characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Symbol

Parameter

Conditions

VIL

VIH

Vhys

VIL

VIH

Vhys

Input low level voltage 1)

Input high level voltage 1)

CMOS ports

Schmitt trigger voltage hysteresis 2)

Input low level voltage 1)

Input high level voltage 1)

G & H ports

Schmitt trigger voltage hysteresis 2)

IINJ(PIN)3)

Injected Current on an I/Os exept

PD7

IINJ(PIN)3) Injected Current on PD7

ΣIINJ(PIN)3)

Total injected current (sum of all I/O

and control pins)

VDD=5V

IL

Input leakage current

VSS≤VIN≤VDD

IS

Static current consumption 4)

Floating input mode

RPU Weak pull-up equivalent resistor 5) VIN=VSS

VDD=5V

CIO

tf(IO)out

tr(IO)out

tw(IT)in

I/O pin capacitance

Output high to low level fall time 1)

Output low to high level rise time 1)

External interrupt pulse time 6)

CL=50pF

Between 10% and 90%

Min

Typ

0.7xVDD

1

2.8

400

80

120

5

25

25

1

Max

0.3xVDD

0.8

+5/-2

+5/-0

± 25

±11

200

250

Unit

V

V

V

mV

mA

µA

kΩ

pF

ns

tCPU

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be

respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD

while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the

corresponding VIN maximum must always be respected

Refer to section 11.2.2 on page 244 for more details.

4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for

example or an external pull-up or pull-down resistor (see Figure 135). Data based on design simulation and/or technology

characteristics, not tested in production.

5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-

scribed in Figure 136). This data is based on characterization results, tested in production at VDD max.

6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

interrupt source.

260/294

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