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ST7PMC2N6B6(2004) 查看數據表(PDF) - STMicroelectronics

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ST7PMC2N6B6 Datasheet PDF : 294 Pages
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ST7MC1/ST7MC2
11.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for VDD, fOSC, and TA.
11.5.1 General Timings
Symbol
Parameter
Conditions
tc(INST)
tv(IT)
Instruction cycle time
Interrupt reaction time 2)
tv(IT) = tc(INST) + 10
fCPU=8MHz
fCPU=8MHz
Min
Typ 1)
Max
2
3
12
250
375
1500
10
22
1.25
2.75
Unit
tCPU
ns
tCPU
µs
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
11.5.2 External Clock Source
Symbol
VOSC1H
VOSC1L
tw(OSC1H)
tw(OSC1L)
tr(OSC1)
tf(OSC1)
IL
Parameter
OSC1 input pin high level voltage
OSC1 input pin low level voltage
OSC1 high or low time 1)
OSC1 rise or fall time 1)
OSCx Input leakage current
Conditions
see Figure 133
VSSVINVDD
Min
Typ
0.7xVDD
VSS
25
Max
VDD
0.3xVDD
Unit
V
ns
5
±1
µA
Figure 133. Typical Application with an External Clock Source
VOSC1H
VOSC1L
90%
10%
tr(OSC1)
tf(OSC1)
tw(OSC1H)
tw(OSC1L)
VDD
OSC2
EXTERNAL
CLOCK SOURCE
OSC1
fOSC
IL
ST7FMC
Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
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