ST7FMC2N6B6(2004) 查看數據表（PDF） - STMicroelectronics

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ST7FMC2N6B6
(Rev.:2004)

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI™

STMicroelectronics 

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)

CONTROL REGISTER 1 (SCICR1)

Read/Write

Reset Value: x000 0000 (x0h)

7

0

R8

T8 SCID M WAKE PCE1) PS PIE

1)This bit has a different function in LIN mode, please

refer to the LIN mode register description.

Bit 7 = R8 Receive data bit 8.

This bit is used to store the 9th bit of the received

word when M=1.

Bit 6 = T8 Transmit data bit 8.

This bit is used to store the 9th bit of the transmit-

ted word when M=1.

Bit 5 = SCID Disabled for low power consumption

When this bit is set the SCI prescalers and outputs

are stopped and the end of the current byte trans-

fer in order to reduce power consumption.This bit

is set and cleared by software.

0: SCI enabled

1: SCI prescaler and outputs disabled

Bit 4 = M Word length.

This bit determines the word length. It is set or

cleared by software.

0: 1 Start bit, 8 Data bits, 1 Stop bit

1: 1 Start bit, 9 Data bits, 1 Stop bit

Note: The M bit must not be modified during a data

transfer (both transmission and reception).

Bit 3 = WAKE Wake-Up method.

This bit determines the SCI Wake-Up method, it is

set or cleared by software.

0: Idle Line

1: Address Mark

Note: If the LINE bit is set, the WAKE bit is de-ac-

tivated and replaced by the LHDM bit

Bit 2 = PCE Parity control enable.

This bit is set and cleared by software. It selects

the hardware parity control (generation and detec-

tion for byte parity, detection only for LIN parity).

0: Parity control disabled

1: Parity control enabled

Bit 1 = PS Parity selection.

This bit selects the odd or even parity when the

parity generation/detection is enabled (PCE bit

set). It is set and cleared by software. The parity

will be selected after the current byte.

0: Even parity

1: Odd parity

Bit 0 = PIE Parity interrupt enable.

This bit enables the interrupt capability of the hard-

ware parity control when a parity error is detected

(PE bit set). The parity error involved can be a byte

parity error (if bit PCE is set and bit LPE is reset) or

a LIN parity error (if bit PCE is set and bit LPE is

set).

0: Parity error interrupt disabled

1: Parity error interrupt enabled

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