ST7FMC2N6B6(2004) 查看數據表（PDF） - STMicroelectronics

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ST7FMC2N6B6
(Rev.:2004)

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI™

STMicroelectronics 

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)

9.5.5.2 Transmitter

The transmitter can send data words of either 8 or

9 bits depending on the M bit status. When the M

bit is set, word length is 9 bits and the 9th bit (the

MSB) has to be stored in the T8 bit in the SCICR1

register.

Character Transmission

During an SCI transmission, data shifts out least

significant bit first on the TDO pin. In this mode,

the SCIDR register consists of a buffer (TDR) be-

tween the internal bus and the transmit shift regis-

ter (see Figure 60).

Procedure

– Select the M bit to define the word length.

– Select the desired baud rate using the SCIBRR

and the SCIETPR registers.

– Set the TE bit to send a preamble of 10 (M=0) or

11 (M=1) consecutive ones (Idle Line) as first

transmission.

– Access the SCISR register and write the data to

send in the SCIDR register (this sequence clears

the TDRE bit). Repeat this sequence for each

data to be transmitted.

Clearing the TDRE bit is always performed by the

following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

The TDRE bit is set by hardware and it indicates:

– The TDR register is empty.

– The data transfer is beginning.

– The next data can be written in the SCIDR regis-

ter without overwriting the previous data.

This flag generates an interrupt if the TIE bit is set

and the I[|1:0] bits are cleared in the CCR register.

When a transmission is taking place, a write in-

struction to the SCIDR register stores the data in

the TDR register and which is copied in the shift

register at the end of the current transmission.

When no transmission is taking place, a write in-

struction to the SCIDR register places the data di-

rectly in the shift register, the data transmission

starts, and the TDRE bit is immediately set.

When a character transmission is complete (after

the stop bit or after the break character) the TC bit

is set and an interrupt is generated if the TCIE is

set and the I[1:0] bits are cleared in the CCR reg-

ister.

Clearing the TC bit is performed by the following

software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

Note: The TDRE and TC bits are cleared by the

same software sequence.

Break Characters

Setting the SBK bit loads the shift register with a

break character. The break character length de-

pends on the M bit (see Figure 61)

As long as the SBK bit is set, the SCI sends break

characters to the TDO pin. After clearing this bit by

software, the SCI inserts a logic 1 bit at the end of

the last break character to guarantee the recogni-

tion of the start bit of the next character.

Idle Line

Setting the TE bit drives the SCI to send a pream-

ble of 10 (M=0) or 11 (M=1) consecutive ‘1’s (idle

line) before the first character.

In this case, clearing and then setting the TE bit

during a transmission sends a preamble (idle line)

after the current word. Note that the preamble du-

ration (10 or 11 consecutive ‘1’s depending on the

M bit) does not take into account the stop bit of the

previous character.

Note: Resetting and setting the TE bit causes the

data in the TDR register to be lost. Therefore the

best time to toggle the TE bit is when the TDRE bit

is set i.e. before writing the next byte in the SCIDR.

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