PCA8538UG(2014) 查看數據表（PDF） - NXP Semiconductors.

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PCA8538UG
(Rev.:2014)

Automotive 102 x 9 Chip-On-Glass LCD segment driver

NXP Semiconductors. 

NXP Semiconductors

PCA8538

Automotive 102 x 9 Chip-On-Glass LCD segment driver

8.5.2.1

Line inversion mode (driving scheme A)

In line inversion mode, the DC value is compensated every nth line. Changing the

inversion mode to line inversion mode reduces the possibility for flickering but increases

the power consumption (see example waveforms in Figure 25 on page 45 to Figure 32 on

page 52)

8.5.2.2 Frame inversion mode (driving scheme B)

In frame inversion mode, the DC value is compensated across two frames and not within

one frame (see example waveform in Figure 33 on page 53). Changing the inversion

mode to frame inversion reduces the power consumption, therefore it is useful when

power consumption is a key point in the application.

Frame inversion may not be suitable for all applications. The RMS voltage across a

segment is better defined, however since the switching frequency is reduced there is

possibility for flicker to occur.

8.5.3 Command: Display-ctrl

The Display-ctrl command enables or disables the display.

Table 22. Display-ctrl - display on and off switch command bit description

Bit

Symbol

Value

Description

-

R/W

0

fixed value

-

RS[1:0]

00

fixed value

7 to 1 -

0011100

fixed value

0

DE

display control

0[1]

display disabled

1

display enabled

[1] Default value.

8.6 Clock and frame frequency command

8.6.1 Oscillator

The internal logic and LCD drive signals of the PCA8538 are timed by the clock frequency

fclk, which is either internally generated by an on-chip oscillator circuit or externally

supplied.

The clock frequency fclk determines the internal data flow of the device that includes the

transfer of display data from the display RAM to the display segment outputs and the

generation of the LCD frame frequency.

8.6.2 External clock

When an external clock is used, the input pin OSC must be connected to VDD1. The clock

must be supplied to the CLK pin and must have an amplitude equal to the VDD1 voltage

supplied to the chip and be referenced to VSS1.

Remark: If an external clock is used, then this clock signal must always be supplied to the

device. Removing the clock may freeze the LCD in a DC state, which is not suitable for the

liquid crystal. Removal of the clock is possible when following the correct procedures as

described in Section 8.8.4 on page 27.

PCA8538

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 26 September 2014

© NXP Semiconductors N.V. 2014. All rights reserved.

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