CS8422-DNZR 查看數據表（PDF） - Cirrus Logic

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CS8422-DNZR

24-bit, 192-kHz, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver

Cirrus Logic 

CS8422

The first option allows access directly through registers. The first 5 bytes of the Channel Status block are

decoded into the “Channel Status Registers (23h - 2Ch)”. Registers 23h-27h contain the A channel status

data. Registers 28h-2Ch contain the B channel status data.

Received Channel Status (C), User (U), and EMPH bits may also be serial outputs to the GPO pins by

appropriately setting the GPOxSEL bits in the “GPO Control 1 (05h)” registers. OLRCK and RCBL can be

made available to qualify the C and U data output. In serial port slave mode, VLRCK and RCBL can be

made available to qualify the C and U data output. VLRCK is a virtual word clock, equal to the receiver

recovered sample rate, that can be used to frame the C/U output. VLRCK and RCBL are available through

the GPO pins. Figure 19 illustrates timing of the C and U data, and their related signals. To recover serial

C-data or U-data with either OLRCK1 or OLRCK2, the corresponding serial port must be directly sourced

by the AES3 receiver (not the SRC).

To source an SDOUT signal directly from the RX receiver, the receiver should be set in master mode in

order to recover the received data. In this configuration, the SDOUT signal sourced from the receiver will

toggle at the AES frame rate. If the RX receiver is set to slave mode, the user must ensure that its asso-

ciated input OLRCK signal is externally synchronized to the input S/PDIF stream in order to recover the

received data. In both configurations, VLRCK is equal to the OLRCK signal associated with the serial port

used to clock the recovered receiver data.

When both SDOUTs are sourced from the RX receiver, VLRCK will equal OLRCK1. When both SDOUTs

are sourced from the SRC, then VLRCK will equal the recovered AES frame rate, not OLRCK.

SDOUT1

RX

RX

SRC

SRC

SDOUT2

RX

SRC

RX

SRC

VLRCK

OLRCK1

OLRCK1

OLRCK2

AES FRAMES

Table 1. VLRCK Behavior

COMMENT

see (Note 4)

see (Note 4)

see (Note 4)

see (Note 6)

The user may also access all of the C and U bits directly from the output data stream (SDOUT) by setting

bits SOFSELx[1:0]=11 (AES3 Direct mode) in “Serial Audio Output Data Format - SDOUT1 (0Ch)” or “Se-

rial Audio Output Data Format - SDOUT2 (0Dh)”. The appropriate bits can be stripped from the SDOUT

signal by external control logic such as a DSP or microcontroller. AES3 Direct mode is only valid if the

serial port in question is directly sourced by the AES3 receiver (not the SRC).

If the incoming User data bits have been encoded as Q-channel subcode, the data is decoded, buffered,

and presented in 10 consecutive register locations located in “Q-Channel Subcode (19h - 22h)” register.

An interrupt may be enabled to indicate the decoding of a new Q-channel block, which may be read

through the “Interrupt Status (14h)” register.

The encoded Channel Status bits which indicate sample word length are decoded according to

AES3-2003 or IEC 60958. The number of auxiliary bits are reported in bits 7 through 4 of the “Receiver

Channel Status (11h)”.

DS692F1

35

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