CS8422-DNZR 查看數據表（PDF） - Cirrus Logic
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CS8422-DNZR Datasheet PDF : 82 Pages
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CS8422
determines what the output sample rate will be based on the MCLK selected for SDOUT1, as shown in the
hardware control pin descriptions shown above. For SDOUT2, the output sample rate is dictated by the in-
coming AES3 data, and the master mode clock ratio determines the frequency of RMCK relative to the in-
coming AES3 sample rate. Note: if TDM Mode is selected for SDOUT1, then SDOUT1 cannot be set to
“Master, Fso = MCLK/128”.
SAOF pin
32.4 k ± 1% to GND
16.2 k ± 1% to GND
8.06 k ± 1% to GND
4.02 k ± 1% to GND
1.96 k ± 1% to GND
1.0 k + 1% to GND
32.4 k ± 1% to VL
16.2 k ± 1% to VL
8.06 k ± 1% to VL
4.02 k ± 1% to VL
1.96 k ± 1% to VL
1.0 k + 1% to VL
SDOUT1 Data Format
I²S 24-bit data
I²S 20-bit data
I²S 16-bit data
Left-Justified 24-bit data
Left-Justified 20-bit data
Left-Justified 16-bit data
Right-Justified 24-bit data
(Master mode only)
Right-Justified 20-bit data
(Master mode only)
Right-Justified 16-bit data
(Master mode only)
TDM Mode 24-bit data
TDM Mode 20-bit data
TDM Mode 16-bit data
SDOUT2 Data Format
I²S
I²S
I²S
Left-Justified
Left-Justified
Left-Justified
Right-Justified
(Master mode only)
Right-Justified
(Master mode only)
Right-Justified
(Master mode only)
I²S
I²S
I²S
Table 4. Hardware Mode Serial Audio Format Control
MS_SEL pin
127.0 k ± 1% to GND
63.4 k ± 1% to GND
32.4 k ± 1% to GND
16.2 k ± 1% to GND
8.06 k ± 1% to GND
4.02 k ± 1% to GND
1.96 k ± 1% to GND
1.0 k + 1% to GND
127.0 k ± 1% to VL
63.4 k ± 1% to VL
32.4 k ± 1% to VL
16.2 k ± 1% to VL
8.06 k ± 1% to VL
4.02 k ± 1% to VL
1.96 k ± 1% to VL
1.0 k + 1% to VL
SDOUT1
Slave
Master, Fso = MCLK/128
Master, Fso = MCLK/256
Master, Fso = MCLK/512
Slave
Master, Fso = MCLK/128
Master, Fso = MCLK/256
Master, Fso = MCLK/512
Slave
Master, Fso = MCLK/128
Master, Fso = MCLK/256
Master, Fso = MCLK/512
Slave
Master, Fso = MCLK/128
Master, Fso = MCLK/256
Master, Fso = MCLK/512
SDOUT2
Slave
RMCK = 256 x Fsi
Master Mode,
RMCK = 128 x Fsi
Master Mode,
RMCK = 256 x Fsi
Master Mode,
RMCK = 512 x Fsi
Table 5. Hardware Mode Serial Audio Port Clock Control
DS692F1
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