CS8422-DNZR 查看數據表（PDF） - Cirrus Logic

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CS8422-DNZR

24-bit, 192-kHz, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver

Cirrus Logic 

1.2 Hardware Mode

CS8422

RXP0 1

RXN0 2

VA 3

AGND 4

RXP1 5

RXN1 6

SAOF 7

MS_SEL 8

32 31 30 29 28 27 26 25

Thermal Pad

Top-Down View

32-Pin QFN Package

24 OSCLK2

23 SDOUT2

22 VL

21 DGND

20 VD_FILT

19 V_REG

18 TX/U

17 C

9 10 11 12 13 14 15 16

Pin Name

RXP/RXN[1:0]

VA

AGND

SAOF

MS_SEL

NV/RERR

V/AUDIO

XTI

XTO

Pin #

Pin Description

1

2

5

6

AES3/SPDIF Input (Input) - Differential receiver inputs carrying AES3 or S/PDIF encoded digital

data. RXP[1:0] comprise the non-inverting inputs of the differential input multiplexer; and RXN[1:0]

comprise the inverting inputs of the input multiplexer. Unused inputs should be tied to AGND.

Analog Power (Input) - Analog power supply, nominally +3.3 V. Care should be taken to ensure that

3 this supply is as noise-free as possible, as noise on this pin will directly affect the jitter performance of

the recovered clock.

4

Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be

connected to a common ground area under the chip.

7

Serial Audio Output Format Select (Input) - Used to select the serial audio output format after RST

is released. See Table 4 on page 41 for format settings.

8

Master/Slave Select (Input) - Used to select Master or Slave settings for the output serial audio ports

after RST is released. See Table 5 on page 41 for format settings.

9

Non-Validity Receiver Error/Receiver Error (Output) - Receiver error indicator. NVERR is output by

default, RERR is selected by a 20 k resistor to VL.

Validity Data/AUDIO (Output) - If a 20 k pull-down is present on this pin, it will output serial Validity

10 data from the AES3 receiver, clocked by the rising and falling edges of OLRCK2 in master mode. If a

20 k pull-up is present, the pin will be low when valid linear PCM data is present at the AES3 input.

11

Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “SRC Master Clock”

on page 38.

12 Crystal Out (Output) - Crystal output for Master clock. See “SRC Master Clock” on page 38.

DS692F1

11

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