CS7620-IQ 查看數據表（PDF） - Cirrus Logic

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CS7620-IQ

CCD Imager Analog Processor

Cirrus Logic 

CS7620

RST - Reset pin, negative true

Pin 38

May be connected to external power-on-reset-circuit. Supplied by VDDA2.

SCAN_MODE - Test

Pin 17

Supplied by VDD_RING.

SCLK - Serial bus clock signal

Pin 6

Supplied by VDD_RING.

SDATI - Serial bus data input signal

Pin 7

Supplied by VDD_RING.

SEN - Serial bus enable signal-chip select (active low)

Pin 9

Supplied by VDD_RING.

TEST - Test enable pin

Pin 16

Supplied by VDD_RING.

5.4 CMOS Analog Input

AIN - Video data input from CCD

Pin 23

Supplied by VDDA1.

BG_RES - Band-gap resistor

Pin 21

Supplied by VDDA1. A 10 kΩ resistor should be connected between BG_RES

and GNDA1.

5.5 CMOS Analog Output

DAC_OUT[1:2] - General purpose Digital-to-Analog converter output

Pins 18 and 19

Supplied by VDDA1.

5.6 CMOS 4 mA Output

CLKO - Clock = output

Pin 52

Signal on this pin can either be the pixel clock output or data_valid signal out-

put. Supplied by VDD_RING.

DOUT[0:12] - Digitized CCD data output

Pins 53-64, and 1

DOUT0 is LSB. Supplied by VDD_RING.

SDATO - Serial bus data output signal

Pin 8

Supplied by VDD_RING.

HSYNC - Horiz sync (active low)

Pin 12

Supplied by VDD_RING.

RD_OUT - Readout signal (active low)

Pin 13

Supplied by VDD_RING.

RG - Reset gate clock pulse for CCD

Pin 37

Supplied by VDDA3.

66

DS301PP2

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