CS7620-IQ 查看數據表（PDF） - Cirrus Logic
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CS7620-IQ Datasheet PDF : 70 Pages
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CS7620
Bit
Mnemonic
Function
4
clk_divide4
Clock Divider: The master clock frequency can be an integer multiple of the
3
clk_divide3
pixel clock rate. This register contains the number by which to divide the mas-
2
clk_divide2
ter clock frequency in order to get the pixel clock frequency. If a ‘0’ is pro-
grammed here, the divider is bypassed and the master clock is assumed to be
1
clk_divide1
at the pixel rate.
0
clk_divide0
4.53 DAC #1 Control
Default = 00h; Read/Write (address 40h)
Bit Number
Bit Name
Default
7
dac_cntl17
0
6
dac_cntl16
0
5
dac_cntl15
0
4
dac_cntl14
0
3
dac_cntl13
0
2
dac_cntl12
0
1
dac_cntl11
0
0
dac_cntl10
0
Bit
Mnemonic
Function
7
dac_cntl17
DAC#1 Control: This is the digital input code to the general purpose DAC#1
6
dac_cntl16
which will then be converted into the analog current output. Each LSB in this
5
dac_cntl15
word will increment the output by ~8.7 µA in low current mode and ~34 µA in
high current mode.
4
dac_cntl14
3
dac_cntl13
2
dac_cntl12
1
dac_cntl11
0
dac_cntl10
4.54 DAC #2 Control
Default = 00h; Read/Write (address 41h)
Bit Number
Bit Name
Default
7
dac_cntl27
0
6
dac_cntl26
0
5
dac_cntl25
0
4
dac_cntl24
0
3
dac_cntl23
0
2
dac_cntl22
0
1
dac_cntl21
0
0
dac_cntl20
0
Bit
Mnemonic
Function
7
dac_cntl27
DAC #2 Control: This is the digital input code to the general purpose DAC#2
6
dac_cntl26
which will then be converted into the analog current output. Each LSB in this
5
dac_cntl25
word will increment the output by ~8.7 µA in low current mode and ~34 µA in
high current mode.
4
dac_cntl24
3
dac_cntl23
2
dac_cntl22
1
dac_cntl21
0
dac_cntl20
62
DS301PP2
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