CS7620-IQ 查看數據表（PDF） - Cirrus Logic

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CS7620-IQ

CCD Imager Analog Processor

Cirrus Logic 

CS7620

4.34 Horizontal Timing Control - Analog Delays

Default = 00h; Read/Write (address 2Dh)

Bit Number

Bit Name

Default

7

6

Resrved

-

-

5

phase_h1

0

4

phase_h0

0

3

rgf_reg1

0

2

rgf_reg0

0

1

rgr_reg1

0

0

rgr_reg0

0

Bit

Mnemonic

Function

7:6

-

Reserved

Phase Shift of H1-H4 Pulses: This register allows for minor shifts in the

phases of H1-H4. This can help to optimize the sampling time of the CCD in-

5

phase_h1

put signal. 1 unit of delay is ~1.5 ns. This should be used for final adjustments

only, with large adjustments done through the selection of the appropriate

clock phases for each edge. All four horizontal clocks shift together when this

register is used.

4

phase_h0

0 - no shift

1 - 1.5 ns shift

2 - 3.0 ns shift

3 - 4.5 ns shift

RG Falling Edge Phase Shift: This register allows for minor shifts in the

3

rgf_reg1

phase of the falling edge of RG. 1 unit of delay is ~1.5 ns.

2

rgf_reg0

0 - no shift

1 - 1.5 ns shift

2 - 3.0 ns shift

3 - 4.5 ns shift

RG Rising Edge Phase Shift: This register allows for minor shifts in the

1

rgr_reg1

phase of the rising edge of RG. 1 unit of delay is ~1.5 ns.

0

rgr_reg0

0 - no shift

1 - 1.5 ns shift

2 - 3.0 ns shift

3 - 4.5 ns shift

52

DS301PP2

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