CS7620 查看數據表（PDF） - Cirrus Logic
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CS7620 Datasheet PDF : 70 Pages
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CS7620
4.5 Operation Control 2
Default = 04h; Read/Write (address 07h).
Bit Number
Bit Name
Default
7
pol_hsyncb
0
6
pol_rd_outb
0
5
dac2_mode
0
4
dac1_mode
0
3
fs_lvl1
0
2
fs_lvl0
1
1
gain_cal1
0
0
gain_cal2
0
Bit
Mnemonic
Function
Hsync Polarity: The HSYNC signal output from the chip defaults to be high
when data is being shifted out of the CCD and low during all other times (the
vertical shift time of each line and idle times). This polarity may be swapped
7
pol_hsyncb
with this bit so that HSYNC is low when data is being shifted out and high all
other times.
0 - HSYNC is high during horizontal data read out
1 - HSYNC is low during horizontal data read out
Rd_Out Polarity: The RD_OUT signal output from the chip defaults to be low
when the CCD data readout is being performed and high when not reading out
data from the CCD. The polarity of this signal may be swapped with this bit so
6
pol_rd_outb
that RD_OUT is high during readout and low when not reading data out. Note
that when this bit is redefined in order to function as a vertical sync signal, this
bit will serve to swap its polarity as well.
Dac #2 Current Mode: There are two modes for the output current of DAC2.
Default mode provides a current range of 2.2 mA for the 8-bit input word. This
5
dac2_mode
will increment the current by ~8.6 µA per LSB code change. The high current
mode can be selected using this bit to change the current range to 8.7 mA for
the 8-bit input word. This will increment the current by ~34 µA per LSB code
change.
Dac #1 Current Mode: There are two modes for the output current of DAC1.
Default mode provides a current range of 2.2 mA for the 8-bit input word. This
4
dac1_mode
will increment the current by ~8.6 µA per LSB code change. The high current
mode can be selected using this bit to change the current range to 8.7 mA for
the 8-bit input word. This will increment the current by ~34 µA per LSB code
change.
3
fs_lvl1
Full Scale Level: This is used to set the full scale input range of the CS7620.
Since CCDs have various saturation levels, it is advantageous to set the full
scale input range of the CS7620 to match the saturation level of the CCD
2
fs_lvl0
used. Table 9 shows the full scale level choices
Gain Calibration #1: A calibration of the gain stages is required to insure a
monotonic digital output. In default (‘0’), this calibration is automatically done
1
gain_cal1
after a chip reset and after coming up from power down mode. If the recalibra-
tion after power down is not desired, this bit can be written with a ‘1’ to force
a calibration only after a chip reset.
Gain Calibration #2: A calibration of the gain stages is required to insure a
monotonic digital output. This calibration is transparent to the user. However,
0
gain_cal2
if the user wishes to force a calibration to occur, he may do so by setting this
bit to ‘1’, which will invoke a gain calibration sequence immediately. This bit
automatically clears itself after a calibration has been initiated.
DS301PP2
31
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