CS5560-ISZ 查看數據表（PDF） - Cirrus Logic
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CS5560-ISZ Datasheet PDF : 32 Pages
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7/31/07
CS5560
Calibration can be initiated in either of two ways. If CAL is high when RST transitions from low to high, a
calibration cycle will be performed. When calibration is performed, the offset and full-scale points of the
converter are calibrated. A calibration cycle takes 327,680 MCLK cycles. The RDY signal falls upon com-
pletion of reset and calibration sequence. If CAL is held low when RST transitions from low to high, no
calibration will be performed. Calibrations can be initiated any time the converter is idle by taking the CAL
input high. RDY will fall at the end of the calibration cycle. The CAL pin should be returned low when not
being used.
A calibration cycle calibrates the offset and full-scale points of the converter transfer function. When the
offset portion of the calibration is performed, the AIN+ and AIN- pins are disconnected from the input and
shorted internally. The offset of the converter is then measured and a correction factor is stored in the
offset calibration register. Then the voltage reference is internally connected to act as the input signal to
the converter and a gain calibration is performed. The gain correction results are placed in the gain cali-
bration register. The contents of the 24-bit offset and gain registers are used to map the conversion data
prior to its output from the converter. The offset and gain calibration registers can be read and written if
desired. To read or write the calibration registers inside of the converter, the converter must be idle, and
the serial port must be in the SEC mode (SMODE = VLR). Table 1 depicts the commands necessary to
read or write the calibration registers.
Table 1. Offset & Gain Calibration Register Read/Write Commands
Register
Offset Register
Gain Register
Read Command
0x40
0x20
Write Command
0xC0
0XA0
3.1.1 Offset Register
MSB
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
Sign
2-2
2-12
0
0
0
0
0
0
0
0
0
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
2-11
2-24
0
0
0
0
0
0
0
0
0
0
0
0
The offset register maps one for one with the conversion word when the gain register is set to 1 decimal.
After reset all bits are zero.
3.1.2 Gain Register
MSB
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
22
21
20
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
0
0
1
0
0
0
0
0
0
0
0
0
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
LSB
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
0
0
0
0
0
0
0
0
0
0
0
0
The gain register spans from 0 to (8 - 2-21). After reset, bit D22 is 1, all others are 0. This results in a dec-
imal gain value of 1.000....000.
16
DS713A5
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