CS5541 查看數據表（PDF） - Cirrus Logic

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CS5541

Low-Power, Low-Voltage, 24-Bit ∆Σ ADC

Cirrus Logic 

CS5541

erroneous. The OD flag bit will be cleared to logic 0

when the modulator becomes stable.

The Overrange Flag (OF) bit is set to a logic 1 any

time the input signal is: 1) more positive than posi-

tive full scale, 2) more negative than zero (unipolar

mode), 3) more negative than negative full scale

(bipolar mode). It is cleared back to logic 0 when-

ever a conversion word occurs which is not over-

ranged.

The last 24 SCLKs are used to clock data out of the

conversion data register.

Table 2 and Table 3 illustrate the output coding for

the CS5541. Unipolar conversions are output in bi-

nary format and bipolar conversions are output in

two’s complement format.

2.9.9 Digital Filter

The CS5541 includes two digital filters. The first

filter which achieves simultaneous rejection of

50/60 Hz provides single conversion settling at

13.4 SPS throughput or four conversion settling at

53.7 SPS throughput. The second filter which

achieves 16-bit performance provides single con-

version settling at 64.8 SPS throughput or four con-

version settling at 260 SPS throughput.

The first filter (13.4 SPS and 53.7 SPS throughput)

is optimized to yield better than 80 dB rejection be-

tween 47 Hz to 63 Hz (i.e. 80 dB minimum rejec-

tion for both 50 Hz and 60 Hz) when the master

clock is 32.768 kHz. The filter has a response as

shown in Figure 14.

The second filter is optimized for higher through-

put, and does not provide 50 Hz or 60 Hz rejection.

It has a frequency response that is shown in Figure

15.

To ease code development, each filter (13.4 SPS or

64.8 SPS throughput) has a mode that only outputs

fully settled output conversions (every 4th convolu-

tion).

D23

MSB

D11

11

D31 D30

D29

D28

D27

D26

0

1

1

1

1

CH

D22 D21 D20 D19 D18

D17

D16

D15

D14

22

21

20

19

18

17

16

15

14

D10 D9

D8

D7

D6

D5

D4

D3

D2

10

9

8

7

6

5

4

3

2

Table 2. Output Conversion Data Register Description (24 bits + flags)

Unipolar Input Voltage

>(VFS-1.5 LSB)

VFS-1.5 LSB

VFS/2-0.5 LSB

+0.5 LSB

<(+0.5 LSB)

Offset Binary

Bipolar Input Voltage

FFFFFF

FFFFFF

-----

FFFFFE

800000

-----

7FFFFF

000001

-----

000000

000000

>(VFS-1.5 LSB)

VFS-1.5 LSB

-0.5 LSB

-VFS+0.5 LSB

<(-VFS+0.5 LSB)

Table 3. CS5541 24-Bit Output Coding

D25

D24

OD

OF

D13

D12

13

12

D1

D0

1

LSB

Two’s

Complement

7FFFFF

7FFFFF

-----

7FFFFE

000000

-----

FFFFFF

800001

-----

800000

800000

Note: VFS in the table equals the voltage between ground and full scale for the unipolar mode, or the voltage

between ± full scale for the bipolar mode. See text about error flags under overrange conditions.

18

DS500PP1

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