CS5376A(2004) 查看數據表（PDF） - Cirrus Logic

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CS5376A
(Rev.:2004)

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

SWITCHING CHARACTERISTICS

Test Bit Stream (TBS)

TBSCLK

t1

t2

t3

TBSDATA

t4

t5

MCLK

CS5376A

Note: Example timing shown for a 256 kHz output rate and no programmable delays.

Figure 8. TBS Output Clock and Data Timing

Parameter

Symbol Min

Typ

Max Unit

TBS Clock Timing

TBS Clock Period

TBS Clock High Time

TBS Clock Low Time

TBS Data Output Timing

t1

(Note 5)

t2

t3

-

3.906

-

µs

40

-

60

%

40

-

60

%

TBS Data Bit Rate

-

256

-

kbps

TBS Data Rising to TBS Clock Rising Setup Time

t4

TBS Clock Rising to TBS Data Falling Hold Time (Note 6)

t5

60

-

60

-

-

ns

-

ns

5. TBSCLK phase can be delayed in 1/8 increments. The timing diagram shows no TBSCLK delay.

6. TBSDATA can be delayed from 0 to 63 full bit periods. The timing diagram shows no TBSDATA delay.

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