CS5464-IS 查看數據表（PDF） - Cirrus Logic
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CS5464-IS Datasheet PDF : 46 Pages
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CS5464
with a quartz crystal. To reduce circuit cost, two load ca-
pacitors C1 and C2 are integrated in the device, from
XIN to DGND, and XOUT to DGND. PCB trace lengths
should be minimized to reduce stray capacitance. To
drive the device from an external clock source, XOUT
should be left unconnected while XIN is driven by the
external circuitry. There is an amplifier between XIN and
the digital section which provides CMOS level signals.
This amplifier works with sinusoidal inputs so there are
no problems with slow edge times.
The CS5464 can be driven by an external oscillator
ranging from 2.5 to 20 MHz, but the K divider value must
be set such that the internal MCLK will run somewhere
between 2.5 MHz and 5 MHz. The K divider value is set
with the K[3:0] bits in the Configuration Register. As an
example, if XIN = MCLK = 15 MHz, and K is set to 5,
DCLK will equal 3 MHz, which is a valid value for DCLK.
5.12 Event Handler
The INT pin is used to indicate that an internal error or
event has taken place in the CS5464. Writing a logic 1
to any bit in the Mask Register allows the corresponding
bit in the Status Register to activate the INT pin. The in-
terrupt condition is cleared by writing a logic 1 to the bit
that has been set in the Status Register.
The behavior of the INT pin is controlled by the IMODE
and IINV bits of the Configuration Register.
IMODE IINV
INT Pin
0
0
Active-low Level
0
1
Active-high Level
1
0
Low Pulse
1
1
High Pulse
XOUT
C1
Oscillator
Circuit
XIN
DGND
C2
C1 = C2 = 22 pF
Figure 11. Oscillator Connection
Table 5. Interrupt Configuration
If the interrupt output signal format is set for either falling
or rising edge, the duration of the INT pulse will be at
least one DCLK cycle (DCLK = MCLK/K).
5.12.1 Typical Interrupt Handler
The steps below show how interrupts can be handled.
INITIALIZATION:
1) All Status bits are cleared by writing 0xFFFFFF to
the Status Register.
2) The condition bits which will be used to generate
interrupts are then set to logic 1 in the Mask Reg-
ister.
3) Enable interrupts.
22
DS682PP1
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