CS5461-IS 查看數據表（PDF） - Cirrus Logic

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CS5461-IS

Single Phase Bi-Directional Power/Energy IC

Cirrus Logic 

CS5461

7.16 VSAGDuration: Voltage Sag-Detect Duration Level

Address: 24

MSB

LSB

223 222 221 220 219 218 217 216 .....

26

25

24

23

22

21

20

Default** = 0x000000

This Register sets the number of conversions over to accumulate RMS voltage for comparison against the VSA-

GLEVEL. Setting this register to zero will disable the VSAG feature.

7.17 Control Register

Register Address: 28

23

22

21

20

19

18

17

16

15

14

13

12

11

10

FAC

7

6

5

4

3

2

MECH

INTOD

NOCPU

Default** = 0x000000

FAC

1 = enable anti-creep for FOUT pulse output function.

EAC

1 = enable anti-creep for EOUT pulse output function.

STOP

1 = used to terminate the new EEBOOT sequence.

MECH

1 = widens EOUT and EDIR pulses for mechanical counters.

INTOD

1 = Converts INT output to open drain configuration.

NOCPU

1 = saves power by disabling the CPUCLK external drive pin.

NOOSC

1 = saves power by disabling the crystal oscillator circuit.

STEP

1 = enables stepper-motor signals on the EOUT/EDIR pins.

9

EAC

1

NOOSC

8

STOP

0

STEP

DS546F2

39

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