CS5461-IS 查看數據表（PDF） - Cirrus Logic

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CS5461-IS

Single Phase Bi-Directional Power/Energy IC

Cirrus Logic 

CS5461

7.9 Power Offset Register

Address: 14

MSB

LSB

-(20) 2-1

2-2

2-3

2-4

2-5

2-6

2-7

..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

Default** = 0.000

This offset value is added to each power value that is computed for each voltage/current sample pair before

being accumulated in the Energy Register. This register can be used to offset contributions to the energy result

that are caused by undesirable sources of energy that are inherent in the system. This value is in two’s comple-

ment notation.

7.10 Status Register and Mask Register

Address: 15 (Status Register); 26 (Mask Register)

23

22

21

20

19

DRDY

EOUT

EDIR

CRDY

18

17

16

IOR

VOR

15

14

13

12

11

10

9

8

IROR

VROR

EOOR

7

6

5

4

3

2

1

0

VOD

IOD

LSD

VSAG

IC

Default** = 0x000000 (Status Register)

0x000000 (Mask Register)

The Status Register indicates the condition of the chip. In normal operation writing a '1' to a bit will cause the bit

to go to the '0' state. Writing a '0' to a bit will maintain the status bit in its current state. With this feature the user

can simply write to the Status Register to clear the bits that have been seen, without concern of clearing any

newly set bits. Even if a status bit is masked to prevent an interrupt, the status bit will still be set in the Status

Register.

The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in the Mask Register will

allow the corresponding bit in the Status Register to activate the INT pin when the status bit is asserted.

DRDY

Data Ready. When running in single or continuous conversion acquisition mode, this bit will in-

dicate the end of computation cycles. When running calibrations, this bit indicates the end of a

calibration sequence.

EOUT

Indicates that the energy limit has been reached for the EOUT Energy Accumulation Register,

and so this register will be cleared, and one pulse will be generated on the EOUT pin (if en-

abled). If EOUT is asserted, this bit will be cleared automatically just after the beginning of any

subsequent A/D conversion cycle in which no EOUT pulses need to be issued. The bit can also

be cleared by writing to the Status Register. This status bit is set with a maximum frequency of

4 kHz (when MCLK/K is 4.096 MHz). When MCLK/K is not equal to 4.096 MHz, the user should

scale the pulse-rate would be expected with MCLK/K = 4.096 MHz by a factor of 4.096 MHz /

(MCLK/K), to get the actual pulse-rate.

EDIR

Set whenever the EOUT bit is asserted as long as the energy result is negative. Reset/Clear

behavior of the EDIR status bit is similar to the EOUT status bit.

IOR

Current Out of Range. Set when the magnitude of the calibrated current value is too large or

too small to fit in the Instantaneous Current Register.

36

DS546F2

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