CS5461 查看數據表（PDF） - Cirrus Logic
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CS5461 Datasheet PDF : 45 Pages
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CS5461
7. REGISTER DESCRIPTION
1. “Default**” => bit status after power-on or reset
2. Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits.
7.1 Configuration Register
Address: 0
23
22
21
20
19
18
17
16
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Igain
15
14
EWA
13
12
11
10
9
8
IMODE
IINV
EPP
EOP
EDP
7
6
5
4
3
2
1
0
VHPF
IHPF
iCPU
K3
K2
K1
K0
Default** = 0x000001
PC[6:0]
Phase compensation. A 2’s complement number which sets the delay in the voltage channel.
When MCLK=4.096 MHz and K=1, the phase adjustment range is about -2.8 to +2.8 degrees
and each step is about 0.04 degrees (assuming a power line frequency of 60 Hz). If (MCLK / K)
is not 4.096 MHz, the values for the range and step size should be scaled by the factor
4.096MHz / (MCLK / K).
Default setting is 0000000 = 0.0215 degrees phase delay at 60 Hz (when MCLK = 4.096 MHz).
Igain
Sets the gain of the current PGA
0 = gain is 10 (default)
1 = gain is 50
EWA
Allows the EOUT and EDIR pins to be configured as open-collector output pins.
0 = normal outputs (default)
1 = only the pull-down device of the EOUT and EDIR pins are active
[IMODE IINV] Soft interrupt configuration bits. Select the desired pin behavior for indication of an interrupt.
00 = active low level (default)
01 = active high level
10 = falling edge (INT is normally high)
11 = rising edge (INT is normally low)
EPP
Allows the EOUT and EDIR pins to be controlled by the DL0 and DL1 bits. EOUT and EDIR can
also be accessed using the Status Register.
0 = Normal operation of the EOUT and EDIR pins. (default)
1 = EOP and EDP bits control the EOUT and EDIR pins.
EOP
When EPP = 1, EOUT becomes a user defined pin, and EOP sets the value of the EOUT pin.
Default = '0'
EDP
When EPP = 1, EDIR becomes a user defined pin, EDP sets the value of the EDIR pin.
Default = '0'
VHPF
Control the use of the High Pass Filter on the voltage Channel.
0 = High-pass filter disabled (default)
1 = High-pass filter enabled
IHPF
Control the use of the High Pass Filter on the Current Channel.
DS546F2
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