CS5346 查看數據表（PDF） - Cirrus Logic

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CS5346

103 dB, 192 kHz, Stereo Audio ADC with 6:1 Input Mux

Cirrus Logic 

CS5346

7.4 MCLK Frequency - Address 05h

7

Reserved

6

MCLK

Freq2

5

MCLK

Freq1

4

MCLK

Freq0

3

Reserved

2

Reserved

1

Reserved

0

Reserved

7.4.1 Master Clock Dividers (Bits 6:4)

Function:

Sets the frequency of the supplied MCLK signal. See Table 8 for the appropriate settings.

MCLK Divider

MCLK Freq2 MCLK Freq1 MCLK Freq0

÷1

0

0

0

÷ 1.5

0

0

1

÷2

0

1

0

÷3

0

1

1

÷4

1

0

0

Reserved

1

0

1

Reserved

1

1

x

Table 8. MCLK Frequency

7.5 PGAOut Control - Address 06h

7

Reserved

6

PGAOut

5

Reserved

4

Reserved

3

Reserved

2

Reserved

1

Reserved

0

Reserved

7.5.1 PGAOut Source Select (Bit 6)

Function:

This bit is used to configure the PGAOut pins to be either high impedance or PGA outputs. Refer to

Table 9.

PGAOut

0

1

PGAOutA & PGAOutB

High Impedance

PGA Output

Table 9. PGAOut Source Selection

7.6 Channel B PGA Control - Address 07h

7

Reserved

6

Reserved

5

Gain5

4

Gain4

3

Gain3

7.6.1 Channel B PGA Gain (Bits 5:0)

Function:

See “Channel A PGA Gain (Bits 5:0)” on page 33.

2

Gain2

1

Gain1

0

Gain0

32

DS861PP1

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