CS4525(2008) 查看數據表（PDF） - Cirrus Logic

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CS4525
(Rev.:2008)

30 W Digital Audio Amplifier with Integrated ADC

Cirrus Logic 

6.1.5

CS4525

Auxiliary Serial Output

The CS4525 includes a stereo auxiliary serial output which allows an external device to leverage on its

internal signal processing and routing capabilities. The auxiliary serial output can receive its data from any

of the sources shown in the Digital Signal Flow diagram on page 29.

The supported output data routing configurations are shown in Table 6 below. By default, the serial port

is configured to output channels A and B on the auxiliary output data left and right channels respectively.

LChDSel[1:0]

00

01

10

11

Aux Left Channel Data

Channel A

Channel B

Sub Channel

Channel B X-Over LPF

RChDSel[1:0]

00

01

10

11

Aux Right Channel Data

Channel A

Channel B

Sub Channel

Channel B X-Over HPF

Table 6. Auxiliary Serial Port Data Output

The data output on each channel of AUX_SDOUT is set by the LChDSel[1:0] and RChDSel[1:0] bits in

the Aux Port Configuration register. The frequencies of AUX_LRCK and AUX_SCLK will vary based upon

the whether the serial input or analog input is being used and the frequency of the system clock for the

CS4525; the nominal values for these clocks are listed in Table 7. The characteristics of AUX_SCLK,

AUX_LRCK, and AUX_SDOUT are described in the AUX Serial Audio I/O Port Switching Specifications

table on page 22.

Signal

ADC/SP = 0

(Digital Input Mode)

ADC/SP = 1

(Analog Input Mode)

Applied System Clock from either 18.432, 24.576, or 27.000MHz

SYS_CLK or External Crystal

Frequency of LRCK Input

32kHz, 44.1kHz,

96kHz

or 48kHz

Nominal Frequency of AUX_SCLK Frequency of Frequency of

Output

SCLK Input SCLK Input / 2

Nominal Frequency of AUX_LRCK Frequency of Frequency of

Output

LRCK Input LRCK Input / 2

18.432MHz 24.576MHz 27.000MHz

Not Applicable

2.304MHz 3.072MHz 3.375MHz

48kHz

48kHz 52.734kHz

Table 7. Nominal Switching Frequencies of the Auxiliary Serial Output

The auxiliary port can be enabled using the EnAuxPort bit. When enabled, the port operates as a master

and clocks out data in the format dictated by the AuxI²S/LJ bit. When disabled, the AUX_LRCK,

AUX_SCLK, and AUX_SDOUT pins continuously drive a logic ‘0’. It should be noted that when the

CS4525 is configured for analog input, the AUX_LRCK, AUX_SCLK, and AUX_SDOUT pins will contin-

uously drive a logic ‘0’ if either the PDnADC bit or PDnAll bit is set.

Referenced Control

Register Location

EnAuxPort ........................... “Enable Aux Serial Port (EnAuxPort)” on page 72

LChDSel[1:0]....................... “Aux Serial Port Left Channel Data Select (LChDSel[1:0])” on page 73

RChDSel[1:0] ...................... “Aux Serial Port Right Channel Data Select (RChDSel[1:0])” on page 72

AuxI²S/LJ............................. “Aux/Delay Serial Port Digital Interface Format (AuxI²S/LJ)” on page 72

PDnADC.............................. “Power Down ADC (PDnADC)” on page 88

PDnAll ................................. “Power Down (PDnAll)” on page 89

DS726PP3

43

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