CS43L42 查看數據表（PDF） - Cirrus Logic

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CS43L42

Low Voltage, Stereo DAC with Headphone Amp

Cirrus Logic 

CS43L42

LRCK

SCLK

Left Channel

Right Channel

SDATA 1 0

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

32 clocks

Internal SCLK Mode

Right Justified, 18-Bit Data

INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128

INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

External SCLK Mode

Right Justified, 18-Bit Data

Data Valid on Rising Edge of SCLK

SCLK Must Have at Least 36 Cycles per LRCK Period

Figure 25. CS43L42 Control Port Mode - Serial Audio Format 6

LRCK

SCLK

SDATA

Left Channel

MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB

Right Channel

MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB

Internal SCLK Mode

I2S, Up to 24-Bit data and INT SCLK = 64 Fs if

MCLK/LRCK = 512, 256 or 128

I2S, Up to 24-Bit data and INT SCLK = 48 Fs if

MCLK/LRCK = 384 or 192

External SCLK Mode

I2S, up to 24-Bit Data

Data Valid on Rising Edge of SCLK

Figure 26. CS43L42 Stand Alone Mode - Serial Audio Format 0

LRCK

SCLK

SDATA

Left Channel

M SB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LS B

Right Channel

M SB -1 -2 -3 -4 +5 +4 +3 +2 +1 LS B

Internal SCLK Mode

Left Justified, up to 24-Bit Data

INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128

INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

External SCLK Mode

Left Justified, up to 24-Bit Data

Data Valid on Rising Edge of SCLK

Figure 27. CS43L42 Stand Alone Mode - Serial Audio Format 1

36

DS481PP2

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