CS43L42 查看數據表（PDF） - Cirrus Logic

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CS43L42

Low Voltage, Stereo DAC with Headphone Amp

Cirrus Logic 

CS43L42

LRCK

SCLK

Left Channel

Right Channel

SDATA 0

23 22 21 20 19 18

76543210

23 22 21 20 19 18

76543210

32 clocks

Internal SCLK Mode

Right Justified, 24-Bit Data

INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128

INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

External SCLK Mode

Right Justified, 24-Bit Data

Data Valid on Rising Edge of SCLK

SCLK Must Have at Least 48 Cycles per LRCK Period

Figure 22. CS43L42 Control Port Mode - Serial Audio Format 3

LRCK

SCLK

Left Channel

Right Channel

SDATA 1 0

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

32 clocks

Internal SCLK Mode

Right Justified, 20-Bit Data

INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128

INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

External SCLK Mode

Right Justified, 20-Bit Data

Data Valid on Rising Edge of SCLK

SCLK Must Have at Least 40 Cycles per LRCK Period

Figure 23. CS43L42 Control Port Mode - Serial Audio Format 4

LRCK

SCLK

Left Channel

Right Channel

SDATA

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

32 clocks

Internal SCLK Mode

Right Justified, 16-Bit Data

INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128

INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

External SCLK Mode

Right Justified, 16-Bit Data

Data Valid on Rising Edge of SCLK

SCLK Must Have at Least 32 Cycles per LRCK Period

Figure 24. CS43L42 Control Port Mode - Serial Audio Format 5

DS481PP2

35

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