CS43L42 查看數據表（PDF） - Cirrus Logic

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CS43L42

Low Voltage, Stereo DAC with Headphone Amp

Cirrus Logic 

CS43L42

6. APPLICATIONS

6.1 Grounding and Power Supply

Decoupling

As with any high resolution converter, the

CS43L42 requires careful attention to power sup-

ply and grounding arrangements to optimize per-

formance. Figure 6 shows the recommended power

arrangement with VA, VA_HP, VA_LINE and VL

connected to clean supplies. Decoupling capacitors

should be located as close to the device package as

possible. If desired, all supply pins may be con-

nected to the same supply, but a decoupling capac-

itor should still be used on each supply pin.

6.2 Clock Modes

The CS43L42 operates in one of two clocking

modes. Base Rate Mode supports input sample

rates up to 50 kHz, and High Rate Mode supports

input sample rates up to 100 kHz, see Table 10 and

11. All clock modes use 64x oversampling.

6.3 De-Emphasis

The CS43L42 includes on-chip digital de-empha-

sis. Figure 30 shows the de-emphasis curve for Fs

equal to 44.1 kHz. The frequency response of the

de-emphasis curve will scale proportionally with

changes in sample rate, Fs.

The de-emphasis feature is included to accommo-

date older audio recordings that utilize pre-empha-

sis equalization as a means of noise reduction.

6.4 Recommended Power-up Sequence

1) Hold RST low until the power supply, master

clock and left/right clock are stable. In this

state, the control port is reset to its default set-

tings and VQ_HP and VQ_LINE will remain

low. Set the CP/SA pin at this time.

2) Bring RST high. The device will remain in a

low power state and latch CP/SA, and VQ_HP

and VQ_LINE remain low. If CP/SA is high,

the control port will be accessible at this time

and the desired register settings can be loaded

while keeping the PDN bit set to 1. If CP/SA is

low, the device will begin the stand-alone pow-

er-up sequence

3) (For Control Port Mode) Once the registers are

configured as desired, set the PDN bit to 0, ini-

tiating the power-up sequence. This requires

approximately 50 µS when the PopGuard®

Transient Control (POR) bit is set to 0. If the

POR bit is set to 1, see PopGuard® Transient

Control for total power-up timing.

6.5 PopGuard® Transient Control

The CS43L42 uses PopGuard® technology to min-

imize the effects of output transients during pow-

er-up and power-down. This technique minimizes

the audio transients commonly produced by sin-

gle-ended, single-supply converters when it is im-

plemented with external DC-blocking capacitors

connected in series with the audio outputs.

When the device is initially powered-up, the audio

outputs, AOUTA, AOUTB, HP_A and HP_B are

clamped to GND. Following a delay of approxi-

mately 1000 sample periods, each output begins to

ramp toward the quiescent voltage. Approximately

10,000 left/right clock cycles later, the outputs

reach VQ_LINE and VQ_HP respectively, and audio

output begins. This gradual voltage ramping allows

time for the external DC-blocking capacitor to

charge to the quiescent voltage, minimizing the

power-up transient.

To prevent transients at power-down, the device

must first enter its power-down state. When this oc-

curs, audio output ceases and the internal output

buffers are disconnected from AOUTA, AOUTB,

HP_A and HP_B. In their place, a soft-start current

sink is substituted which allows the DC-blocking

capacitors to slowly discharge. Once this charge is

dissipated, the power to the device may be turned

off, and the system is ready for the next power-on.

DS481PP2

29

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