CS43L42 查看數據表（PDF） - Cirrus Logic

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CS43L42

Low Voltage, Stereo DAC with Headphone Amp

Cirrus Logic 

CS43L42

DEM0 and DEM1

(Stand-Alone Mode)

VL

MCLK

SCL/CCLK

(Control Port Mode)

SDA/CDIN

(Control Port Mode)

4 and 5

De-emphasis Control (Input) - Selects the appropriate digital filter to maintain the standard

15 µs/50 µs digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (see Fig-

ure 30) When using Internal Serial Clock Mode, Pin 5 is available for de-emphasis control,

DEM1, and all de-emphasis filters are available. When using External Serial Clock Mode,

Pin 5 is not available for de-emphasis use and only the 44.1 kHz de-emphasis filter is avail-

able. (see Table 9)

Note: De-emphasis is not available in High-Rate Mode.

DEM1

0

0

1

1

Internal SCLK

DEMO

DESCRIPTION

0 Disabled

1 44.1kHz

0 48kHz

1 32kHz

External SCLK

DEMO

DESCRIPTION

0

Disabled

1

44.1 kHz

Table 9. Stand Alone De-Emphasis Control

6

Interface Power (Input) - Digital interface power supply. Typically 1.8 to 3.3 VDC.

7

Master Clock (Input) - Frequency must be either 256x, 384x, 512x, 768x or 1024x the input

sample rate in Base Rate Mode (BRM) and 128x, 192x, 256x or 384x the input sample rate

in High Rate Mode (HRM). Note that some multiplication factors require setting the

MCLKDIV bit (see Master Clock DIVIDE ENABLE (mclkdiv)). Tables 10 and 11 illustrate

several standard audio sample rates and the required master clock frequencies.

Sample Rate

(kHz)

32

44.1

48

64

88.2

96

128x

4.0960

5.6448

6.1440

8.1920

11.2896

12.2880

MCLK (MHz)

HRM

192x

256x*

6.1440

8.1920

8.4672

11.2896

9.2160

12.2880

12.2880

16.3840

16.9344

22.5792

18.4320

24.5760

384x*

12.2880

16.9344

18.4320

24.5760

33.8688

36.8640

* Requires MCLKDIV bit = 1 in Mode Control 2 register (address 0Bh).

Table 10. HRM Common Clock Frequencies

Sample Rate

(kHz)

32

44.1

48

256x

8.1920

11.2896

12.2880

384x

12.2880

16.9344

18.4320

MCLK (MHz)

BRM

512x

16.3840

22.5792

24.5760

768x*

24.5760

32.7680

36.8640

1024x*

32.7680

45.1584

49.1520

* Requires MCLKDIV bit = 1 in Mode Control 2 register (address 0Bh).

Table 11. BRM Common Clock Frequencies

8

Serial Control Interface Clock (Input) - Clocks the serial control data into or out of

SDA/CDIN.

9

Serial Control Data I/O (Input/Output) - In Two-Wire mode, SDA is a data I/O line. CDIN is

the input data line for the control port interface in SPI mode.

DS481PP2

27

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