CS4226 查看數據表（PDF） - Cirrus Logic
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CS4226 Datasheet PDF : 37 Pages
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CS4226
3.6 Output Attenuator Data Byte (04h, 05h, 06h, 07h, 08h, 09h)
B7
B6
B5
B4
B3
B2
B1
B0
0
ATT6
ATT5
ATT4
ATT3
ATT2
ATT1
ATT0
ATT6-ATT0
Sets attenuator level
0 - No attenuation
127 - 127 dB attenuation
ATT0 represents 1.0 dB of attenuation
This register defaults to 7Fh.
3.7 DAC Status Report Byte (Read Only) (0Ah)
B7
B6
B5
B4
B3
B2
B1
B0
0
-
ACC6
ACC5
ACC4
ACC3
ACC2
ACC1
ACC6-ACC1
Acceptance Bit
1 - New setting is waiting for zero-crossing to be accepted.
0 - ATT6-ATT0 has been accepted.
This register is read-only.
3.8 ADC Control Byte (0Bh)
B7
B6
B5
B4
B3
B2
B1
B0
IS1
IS0
0
AIS1
AIS0
MUTM
MUTR
MUTL
MUTL, MUTR, MUTM - Left, right and mono channel mute control
0 - Normal output level
1 - Selected ADC output muted
AIS1-AIS0
ADC analog input mux control
0 - Selects stereo pair 1
1 - Selects stereo pair 2
2 - Selects stereo pair 3
3 - Differential Input
IS1-IS0
Input mux selection
0 - Stereo ADC output to SDOUT1, Mono ADC output to SDOUT2
1 - Auxiliary Digital Input Port or S/PDIF Receiver to SDOUT1, Mono ADC output to SDOUT2
2 - Auxiliary Digital Input Port or S/PDIF Receiver to SDOUT1, Stereo ADC output to SDOUT2
3 - Not used.
This register defaults to 00h.
26
DS188F4
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