CS4226 查看數據表（PDF） - Cirrus Logic
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CS4226 Datasheet PDF : 37 Pages
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CS4226
3.14 Receiver Status Byte (Read Only) (11h)
B7
B6
B5
B4
B3
B2
B1
B0
CV
0
CRC
LOCK
V
CONF
BIP
PAR
PAR
Parity bit
0 - No error
1 - Error
BIP
Biphase bit
0 - No error
1 - Error
CONF
Confidence bit
0 - No error
1 - Error
V
Validity bit
0 - No error
1 - Error
LOCK
PLL lock bit
0 - PLL locked
1 - Out of lock
CRC
Cyclic Redundancy check bit
0 - No error
1 - Error on either channel
CV
Channel status validity
0 - Valid
1 - Not valid, data is updating
This register is read only.
3.15 Receiver Channel Status Byte (Read Only) (12h, 13h, 14h, 15h, 16h, 17h, 18h, 19h)
B7
B6
B5
B4
B3
B2
B1
B0
CS7
CS6
CS5
CS4
CS3
CS2
CS1
CS0
Byte 12h
Byte 13h
Byte 14h
Byte 15h
Byte 16h
Byte 17h
Byte 18h
Byte 19h
Channel A Status Byte 1
Channel A Status Byte 2
Channel A Status Byte 3
Channel A Status Byte 4
Channel B Status Byte 1
Channel B Status Byte 2
Channel B Status Byte 3
Channel B Status Byte 4
Bit definition changes depending upon PRO bit setting. When CV = 1, these bits are updating and may be invalid.
DS188F4
31
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