CL-PS7111-VC-A 查看數據表（PDF） - Cirrus Logic

零件编号

产品描述 (功能)

生产厂家

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

6.5 I/O Buffer Characteristics

All I/O buffers on the CL-PS7111 are CMOS threshold input bidirectional buffers except the oscillator and

power pads. The output buffer is only enabled during pin test mode for signals that are normally inputs.

All output buffers are disabled during System Test (High-Z) mode. All buffers have a standard CMOS

threshold input stage apart from the Schmitt inputs and CMOS, slew-rate-controlled output stages to

reduce system noise. Table 6-1 defines the I/O buffer output characteristics, which apply across the full

range of voltage and temperature (2.7 V and 0 to +70oC).

Table 6-1. I/O Buffer Output Characteristics

Buffer Type

I/O strength 1

I/O strength 2

Drive Current Propagation Delay (MAX)

± 3 mA

± 12 mA

15 ns

12 ns

Rise Time

(MAX)

20 ns

16 ns

Fall Time

(MAX)

15 ns

13 ns

Load

50 pF

50 pF

NOTES:

1) All propagation delays are specified at 50% VDD to 50% VDD; all rise times are specified as 10% VDD to 90%

VDD, and all fall times are specified as 90% VDD to 10% VDD.

2) Pull-up current = 50 µA typical at VDD = 3.3 volts.

6.6 Test Modes

The CL-PS7111 supports a number of hardware-activated test modes; these are activated by the pin

combinations shown in Table 6-2. All latched signals only alter test modes while NPOR is low, and their

state is latched on the rising edge of NPOR. This allows these signals to be used normally during various

test modes (for example, the NURESET input can be used normally when the device is set into Functional

Test (EPB) mode).

Table 6-2. CL-PS7111 Hardware Test Modes

Test Mode

Normal operation (32-bit boot)

Normal operation (8-bit boot)

Alternative test ROM boot

Oscillator/PLL bypass

Functional Test (EPB)

Oscillator/PLL Test

Pin Test

System Test (all High-Z)

Latched

MEDCHG

0

0

1

X

X

X

X

X

Latched

PE0

0

1

X

X

X

X

X

X

Latched

NURESET

X

X

X

X

1

0

1

0

NTEST0 NTEST1

1

1

1

1

1

1

1

0

0

1

0

1

0

0

0

0

Within each test mode a selection of pins are used as multiplexed outputs or inputs to provide/monitor the

test signals unique to that mode.

September 1997

PRELIMINARY DATA BOOK v2.0

87

ELECTRICAL SPECIFICATIONS

Share Link: