CL-PS7111-VC-A 查看數據表（PDF） - Cirrus Logic

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CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

EXPCLK

NCS[5:0]

Sequential page mode read cycles with minimum wait states

NMOE

A[27:4]

A[3:0]

0

tEXBST

4

tEXBST

8

WORD

D[31:0]

BUS HELD

EXPRDY

t1

tEXRD

t3

t4

DATA IN

t5

t6

t3

t4

DATA IN

t3

t4

DATA IN

Figure 6-2. Expansion and ROM Sequential Read Timing

NOTES:

1) tEXBST = 35 ns at 18.432 MHz and 55 ns maximum at 13.0 MHz for zero wait state page mode access. This

time can be extended by integer multiples of the clock period by either driving EXPRDY low and/or by pro-

gramming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data trans-

fer, if low at this point the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK

need not be referenced when driving EXPRDY but is shown for clarity.

2) Consecutive reads with sequential access enabled are identical except that the sequential access wait state

field is used to determine the number of wait states, and no idle cycles are inserted between successive non

sequential ROM/expansion cycles. This improves performance, so the SQAEN should always be set where

possible.

78

ELECTRICAL SPECIFICATIONS

September 1997

PRELIMINARY DATA BOOK v2.0

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