CL-PS7111-VC-A 查看數據表（PDF） - Cirrus Logic
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CL-PS7111-VC-A Datasheet PDF : 105 Pages
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CL-PS7111
Low-Power System-on-a-Chip
UART operation and line speed are controlled by UBRLCR1 (UART Bit Rate and Line Control register)
and two registers. Three interrupts are generated by UART1, Rx, Tx, and Modem Status Changed. Only
two interrupts are generated by UART2, Rx and Tx. The Rx interrupt asserts when the FIFO becomes half
full or the FIFO is non-empty longer than three character-length times and no more characters are
received. The Tx interrupt asserts when the FIFO buffer reaches half empty. The Modem Status Changed
interrupt for UART1 is generated when any of the modem status bits change state.
Framing and parity errors are detected as each byte is received and pushed onto the Rx FIFO. An overrun
error immediately generates an Rx interrupt. All error bits can be read from the 11-bit-wide data register.
The FIFO can also be programmed to be only one byte deep (such as a conventional UART with double
buffering).
The CL-PS7111 also contains an IrDA SIR protocol encoder. This is a post-processing stage on the out-
put of UART1. This encoder can be optionally switched into the Tx and Rx signals of UART1, allowing
direct drive to an infrared interface. If the SIR protocol encoder is enabled, the UART Txd2 line is held in
the passive state and transitions to the Modem Status Changed, or Rxd2 lines have no effect. The IrDA
output pin is LEDDRV and input from the photodiode is PHDIN.
NOTE: Both UARTs operate similar to the industry standard 16C550. When the CTS deasserts on the UART, it does
not stop shifting the data, relying on software to take appropriate action in response to the interrupt.
Baud rates supported for both UARTs are dependent on frequency of operation. At 18.432 MHz, the
interface supports various baud rates from 115.2 kbps down. The master clock frequency is chosen so
that most of the required data rates are obtainable exactly. When operating with a 13-MHz clock source,
the baud rates generated have a slight error, less than or equal to 0.75%. The rates obtainable from the
13-MHz clock include 9.6, 19.2, 38, 58, and 115.2 kbps. See Table 5-4 on page 66 for available bit rates
in the 13-MHz mode.
3.12 Clocks
There are two clocking options for the CL-PS7111. An on-chip oscillator and PLL provides an 18.432-MHz
master bus clock frequency, using an external 3.6864-MHz crystal. Alternatively, an external 13-MHz
crystal oscillator can be used.
If the 13-MHz clock option is used, connect the clock signal to the EXPCLK pin of the CL-PS7111. This
mode is selected by a strapping option on the PE[2] pin. If this input is high at the rising edge of NPOR,
the 13-MHz mode is selected. In this mode, EXPCLK is an input. If the external clock mode is not selected,
the PLL supplies the clock during the normal mode of operation. The state of PE[2] is latched at the rising
edge of the NPOR reset, and the PE[2] pin is then available for GPIO.
If the CLKENSL bit (SYSCON[25:18]) is set low, then the CLKEN/RUN pin provides the signal that starts
and stops the external clock source supplied to the CL-PS7111 and the DC-DC converter. When this sig-
nal is active (high), it enables the 13-MHz clock to the CL-PS7111, and a low level disables the 13-MHz
clock.
When standby mode is entered in 13-MHz mode, the 13-MHz source is gated out at the pad until it exits
standby. If the CLKENSL bit is low, then the CLKEN signal will be output on the CLKEN/RUN pin and can
disable an external oscillator.
If CLKENSL is set high, then standby mode is immediately exited when a wake-up event or enabled inter-
rupt occurs. If CLKENSL is set high, then the CL-PS7111 sets CLKEN to active after an interrupt or wake-
up event occurs. It then waits between 0.125 and 0.25 sec. to allow an external oscillator to stabilize
before the clock is enabled through the ARM710 CPU. Only a non-masked interrupt (such as a realtime
September 1997
PRELIMINARY DATA BOOK v2.0
35
FUNCTIONAL DESCRIPTION
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