C8051F93X-C8051F92X 查看數據表（PDF） - Silicon Laboratories
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C8051F93X-C8051F92X
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C8051F93X-C8051F92X Datasheet PDF : 330 Pages
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C8051F93x-C8051F92x
SFR Definition 21.8. P0: Port0
Bit
7
6
5
4
3
2
1
0
Name
P0[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Page = All Pages; SFR Address = 0x80; Bit-Addressable
Bit Name
Description
Write
Read
7:0 P0[7:0] Port 0 Data.
0: Set output latch to logic 0: P0.n Port pin is logic
Sets the Port latch logic
LOW.
LOW.
value or reads the Port pin 1: Set output latch to logic 1: P0.n Port pin is logic
logic state in Port cells con- HIGH.
HIGH.
figured for digital I/O.
SFR Definition 21.9. P0SKIP: Port0 Skip
Bit
7
6
5
4
3
2
1
0
Name
P0SKIP[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page= 0x0; SFR Address = 0xD4
Bit Name
Function
7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits.
These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins used
for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
230
Rev. 1.3
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