C8051F93X-C8051F92X 查看數據表（PDF） - Silicon Laboratories

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C8051F93X-C8051F92X

Single/Dual Battery, 0.9–3.6 V, 64/32 kB, SmaRTClock, 10-Bit ADC MCU

Silicon Laboratories 

C8051F93x-C8051F92x

18.1. Power-On (VBAT Supply Monitor) Reset

During power-up, the device is held in a reset state and the RST pin is driven low until VBAT settles above

VPOR. An additional delay occurs before the device is released from reset; the delay decreases as the

VBAT ramp time increases (VBAT ramp time is defined as how fast VBAT ramps from 0 V to VPOR).

Figure 18.3 plots the power-on and VDD monitor reset timing. For valid ramp times (less than 3 ms), the

power-on reset delay (TPORDelay) is typically 3 ms (VBAT = 0.9 V), 7 ms (VBAT = 1.8 V), or 15 ms (VBAT =

3.6 V).

Note: The maximum VDD ramp time is 3 ms; slower ramp times may cause the device to be released from reset

before VBAT reaches the VPOR level.

On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is

set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other

resets). Since all resets cause program execution to begin at the same location (0x0000), software can

read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data

memory should be assumed to be undefined after a power-on reset.

~0.8

VPOR

0.6

VBAT

~0.5

See specification

table for min/max

voltages.

Logic HIGH RST

Logic LOW

TPORDelay

t

TPORDelay

Power-On

Reset

Power-On

Reset

Figure 18.2. Power-Fail Reset Timing Diagram

Rev. 1.3

185

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