C8051F93X-C8051F92X 查看數據表（PDF） - Silicon Laboratories

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C8051F93X-C8051F92X

Single/Dual Battery, 0.9–3.6 V, 64/32 kB, SmaRTClock, 10-Bit ADC MCU

Silicon Laboratories 

C8051F93x-C8051F92x

18. Reset Sources

Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this

reset state, the following occur:

• CIP-51 halts program execution

• Special Function Registers (SFRs) are initialized to their defined reset values

• External Port pins are forced to a known state

• Interrupts and timers are disabled

All SFRs are reset to the predefined values noted in the SFR descriptions. The contents of RAM are

unaffected during a reset; any previously stored data is preserved as long as power is not lost. Since the

stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.

The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled

during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device

exits the reset state.

On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to an internal

oscillator. Refer to Section “19. Clocking Sources” on page 191 for information on selecting and

configuring the system clock source. The Watchdog Timer is enabled with the system clock divided by 12

as its clock source (Section “26.4. Watchdog Timer Mode” on page 316 details the use of the Watchdog

Timer). Program execution begins at location 0x0000.

Px.x

Px.x

Comparator 0

+

-

C0RSEF

VDD/DC+

VBAT

Supply

Monitor

+

-

Enable

Power On

Reset

(wired-OR)

'0'

SmaRTClock RTC0RE

Missing

Clock

Detector

(one-

shot)

EN

PCA

WDT

EN

Reset

Funnel

(Software Reset)

SWRSF

Illegal Flash

Operation

System

Clock

CIP-51

Microcontroller

Core

System Reset

Extended Interrupt

Handler

Power Management

Block (PMU0)

Reset

System Reset

Power-On Reset

Figure 18.1. Reset Sources

RST

184

Rev. 1.3

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